公开(公告)号：US20190287587A1

公开(公告)日：2019-09-19

申请号：US16194834

申请日：2018-11-19

Applicant: SK hynix Inc.

Inventor： Dong Hyun KIM ,  Dae Han KWON ,  Kwan Su SHON ,  Soon Ku KANG ,  Jung Hyun SHIN ,  Doo Bock LEE ,  Yo Han JEONG ,  Eun Ji CHOI ,  Tae Jin HWANG

IPC: G11C7/22 ,  G11C7/10

Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

公开(公告)号：US20180358355A1

公开(公告)日：2018-12-13

申请号：US15855777

申请日：2017-12-27

Applicant: SK hynix Inc.

Inventor： Joong-Ho KIM ,  Hyun Woo KWACK ,  Ki Jong LEE ,  Doo Bock LEE

IPC: H01L27/02 ,  H01L25/065 ,  H02H9/04

CPC classification number: H01L27/0296 ,  H01L25/0657 ,  H01L27/0288 ,  H01L27/0292 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H02H9/046

Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.

公开(公告)号：US20210377483A1

公开(公告)日：2021-12-02

申请号：US16769830

申请日：2018-06-14

Applicant: SK hynix Inc.

Inventor： Chang Hyun KIM ,  Wan Jun ROH ,  Doo Bock LEE ,  Seung Hun LEE ,  Jae Jin LEE ,  Chun Seok JEONG

IPC: H04N5/376 ,  H04N5/05 ,  H04N5/341 ,  H04N5/369 ,  H04N5/372 ,  H04N17/00

Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

公开(公告)号：US20210241814A1

公开(公告)日：2021-08-05

申请号：US16928866

申请日：2020-07-14

Applicant: SK hynix Inc.

Inventor： Doo Bock LEE ,  Yong Suk CHOI

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/4093 ,  G11C8/18

Abstract: A data receiving device includes a clock receiver and a plurality of data receivers. The clock receiver is configured to generate a plurality of internal clock signals from a clock signal and a complementary clock signal based on a switching enable signal. The plurality of data receivers are configured to receive data and a reference voltage and compare the data with the reference voltage in synchronization with the plurality of internal clock signals, respectively, to generate first internal data. Among the plurality of data receivers, a data receiver receiving an internal clock signal, of which a logic level transitions signals when a logic level of the switching enable signal transitions, is configured to change a voltage level of the reference voltage when the logic level of the switching enable signal transitions.

公开(公告)号：US20210082909A1

公开(公告)日：2021-03-18

申请号：US17108824

申请日：2020-12-01

Applicant: SK hynix Inc.

Inventor： Joong-Ho KIM ,  Hyun Woo KWACK ,  Ki Jong LEE ,  Doo Bock LEE

IPC: H01L27/02 ,  H02H9/04

Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.