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    DATA BUFFER AND MEMORY DEVICE HAVING THE SAME
    1.
    发明申请
    DATA BUFFER AND MEMORY DEVICE HAVING THE SAME 有权

    公开(公告)号：US20210057004A1

    公开(公告)日：2021-02-25

    申请号：US17093745

    申请日：2020-11-10

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG

    IPC: G11C7/10 ,  G11C16/26 ,  G11C7/06

    Abstract: There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

    BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS
    3.
    发明申请
    BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS 有权
    半导体器件的缓冲电路

    公开(公告)号：US20150155012A1

    公开(公告)日：2015-06-04

    申请号：US14194006

    申请日：2014-02-28

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG

    IPC: G11C7/02 ,  G11C7/10

    CPC classification number: G11C7/02 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/22 ,  G11C16/28

    Abstract: A buffer circuit of a semiconductor apparatus includes a sensing circuit configured to sense input signals according to a data strobe signal, generate latch control signals, provide the latch control signals at nodes, and remove parasitic components of the nodes in response to a clock signal; and a latch circuit configured to generate and latch output data in response to the latch control signals.

    Abstract translation: 半导体装置的缓冲电路包括：感测电路，被配置为根据数据选通信号感测输入信号，产生锁存控制信号，在节点处提供锁存控制信号，并响应于时钟信号去除节点的寄生分量; 以及锁存电路，被配置为响应于所述锁存控制信号产生和锁存输出数据。

    VOLTAGE GENERATION CIRCUIT AND INPUT BUFFER INCLUDING THE VOLTAGE GENERATION CIRCUIT
    4.
    发明申请
    VOLTAGE GENERATION CIRCUIT AND INPUT BUFFER INCLUDING THE VOLTAGE GENERATION CIRCUIT 有权

    公开(公告)号：US20220308608A1

    公开(公告)日：2022-09-29

    申请号：US17840807

    申请日：2022-06-15

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG ,  Soon Sung AN

    IPC: G05F1/46 ,  H03F3/45 ,  G05F3/24 ,  H03K17/22

    Abstract: A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.

    BUFFER CIRCUIT AND OPERATING METHOD THEREOF
    6.
    发明申请
    BUFFER CIRCUIT AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20210313976A1

    公开(公告)日：2021-10-07

    申请号：US17017009

    申请日：2020-09-10

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG ,  Tai Sik SHIN ,  Dong Shin JO

    IPC: H03K5/156 ,  H03K5/135 ,  H03K5/24 ,  H03K5/02 ,  H03K17/687

    Abstract: An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.

    SIGNAL RECEIVING DEVICE, AND A SEMICONDUCTOR APPARATUS AND A SEMICONDUCTOR SYSTEM INCLUDING THE SIGNAL RECEIVING DEVICE
    7.
    发明申请
    SIGNAL RECEIVING DEVICE, AND A SEMICONDUCTOR APPARATUS AND A SEMICONDUCTOR SYSTEM INCLUDING THE SIGNAL RECEIVING DEVICE 有权

    公开(公告)号：US20210194665A1

    公开(公告)日：2021-06-24

    申请号：US16940111

    申请日：2020-07-27

    Applicant: SK hynix Inc.

    Inventor： Soon Sung AN ,  Kwan Su SHON ,  Jin Ha HWANG

    IPC: H04L7/00 ,  H04L7/02

    Abstract: A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    8.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20210312963A1

    公开(公告)日：2021-10-07

    申请号：US17321601

    申请日：2021-05-17

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG ,  Tai Sik SHIN ,  Dong Shin JO

    IPC: G11C8/06 ,  G11C8/18

    Abstract: An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.

    DATA OUTPUT BUFFER
    10.
    发明申请
    DATA OUTPUT BUFFER 审中-公开

    公开(公告)号：US20200028507A1

    公开(公告)日：2020-01-23

    申请号：US16284758

    申请日：2019-02-25

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG ,  Keun Seon AHN

    IPC: H03K17/687 ,  H03K3/037 ,  G11C7/10

    Abstract: A data output buffer includes a pull-up main driver outputting output data having a high level through an output pad by performing an emphasis operation according to input data, a pull-down main driver outputting the output data having a low level through the output terminal according to the input data, an active inductor controller selectively outputting an inductor activating voltage by detecting a rising or falling period of the input data, and an active inductor selectively performing a de-emphasis operation on the output terminal in response to the inductor activating voltage.

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