公开(公告)号：US10607694B2

公开(公告)日：2020-03-31

申请号：US16124882

申请日：2018-09-07

Applicant: SK hynix Inc.

Inventor： Seung-Gyu Jeong ,  Won-Gyu Shin ,  Jung-Hyun Kwon ,  Do-Sun Hong

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/00 ,  G11C29/52 ,  G11C29/44 ,  G11C29/04 ,  G11C29/42

Abstract: A memory system includes a memory device comprising first to Nth memory regions, wherein N is a natural number equal to or more than 2, and a memory controller suitable for checking numbers of first logic level data which are contained in first to Nth data groups to be written to the memory device, respectively, and writing the first to Nth data groups to the first to Nth memory regions in order based on the checked numbers.

公开(公告)号：US11355190B2

公开(公告)日：2022-06-07

申请号：US16993787

申请日：2020-08-14

Applicant: SK hynix Inc.

Inventor： Seung-Gyu Jeong ,  Jung-Hyun Kwon ,  Won-Gyu Shin ,  Do-Sun Hong

IPC: G11C7/22 ,  G11C13/00 ,  G06F3/06 ,  G11C29/12 ,  G11C7/10 ,  G11C29/36 ,  G11C29/46 ,  G11C11/56

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

公开(公告)号：US10482961B2

公开(公告)日：2019-11-19

申请号：US16007598

申请日：2018-06-13

Applicant: SK hynix Inc.

Inventor： Seung-Gyu Jeong ,  Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin

IPC: G11C11/00 ,  G11C13/00 ,  G06F13/40

Abstract: A memory system includes a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit, wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.

公开(公告)号：US20190188162A1

公开(公告)日：2019-06-20

申请号：US16203591

申请日：2018-11-28

Applicant: SK hynix Inc.

Inventor： Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin ,  Seung-Gyu Jeong

IPC: G06F13/16 ,  G06F3/06

Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.