公开(公告)号：US20180204786A1

公开(公告)日：2018-07-19

申请号：US15408979

申请日：2017-01-18

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Aiza Marie AGUDON ,  Jefferson TALLEDO

IPC: H01L23/495 ,  H01L21/683 ,  H01L23/00 ,  H01L23/58 ,  H01L21/78

Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.

公开(公告)号：US20170263566A1

公开(公告)日：2017-09-14

申请号：US15068752

申请日：2016-03-14

Applicant: STMICROELECTRONICS, INC

Inventor： Rennier RODRIGUEZ ,  Frederick ARELLANO ,  Aiza Marie AGUDON

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/78 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/561 ,  H01L21/78 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81

Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.