-
公开(公告)号：US20190266784A1
公开(公告)日：2019-08-29
申请号：US16280963
申请日：2019-02-20
Inventor： Surinder Pal SINGH , Thomas BOESCH , Giuseppe DESOLI
Abstract: Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes. The data volume sculpting unit is also arranged to identify a 3D volume within the 3D feature map that is dimensionally smaller than the 3D feature map and isolate data from the 3D feature map that is within the 3D volume for processing in a deep learning algorithm.
-
公开(公告)号：US20240220278A1
公开(公告)日：2024-07-04
申请号：US18176323
申请日：2023-02-28
Inventor： Paolo Sergio ZAMBOTTI , Thomas BOESCH , Giuseppe DESOLI , Wolfgang Johann BETZ , David SIORPAES
IPC: G06F9/445
CPC classification number: G06F9/44505
Abstract: A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task. The configuration controller may retrieve the linked list from the memory via a high-speed data bus.
-
公开(公告)号：US20210181828A1
公开(公告)日：2021-06-17
申请号：US17111373
申请日：2020-12-03
Inventor： Nitin CHAWLA , Anuj GROVER , Giuseppe DESOLI , Kedar Janardan DHORI , Thomas BOESCH , Promod KUMAR
IPC: G06F1/3234 , G11C11/413 , G05F3/24 , G06F1/3287 , G06F15/78
Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
-
公开(公告)号：US20200272779A1
公开(公告)日：2020-08-27
申请号：US15931445
申请日：2020-05-13
Inventor： Thomas BOESCH , Giuseppe DESOLI
Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.
-
公开(公告)号：US20190340314A1
公开(公告)日：2019-11-07
申请号：US16517371
申请日：2019-07-19
Inventor： Thomas BOESCH , Giuseppe DESOLI
Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.
-
Patent Agency Ranking
公开(公告)号：US20180189424A1
公开(公告)日：2018-07-05
申请号：US15423292
申请日：2017-02-02
Inventor： Thomas BOESCH , Giuseppe DESOLI
Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.
-
17.发明公开公开(公告)号：US20240220777A1
公开(公告)日：2024-07-04
申请号：US18176315
申请日：2023-02-28
Inventor： Francesca GIRARDI , Giuseppe DESOLI , Ruggero SUSELLA , Thomas BOESCH , Paolo Sergio ZAMBOTTI
IPC: G06N3/0464
CPC classification number: G06N3/0464
Abstract: A hardware accelerator includes functional circuits and streaming engines. An interface is coupled to the plurality of streaming engines. The interface, in operation, performs stream cipher operations on data words associated with data streaming requests. The performing of a stream cipher operation on a data word includes generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines and an address associated with the data word, and XORing the generated mask with the data word. The hardware accelerator may include configuration registers to store configuration information indicating a respective security state associated with functional circuits and streaming engine of the hardware accelerator, which may be used to control performance of operations by the hardware accelerator.
-
公开(公告)号：US20240012871A1
公开(公告)日：2024-01-11
申请号：US17859769
申请日：2022-07-07
Inventor： Antonio DE VITA , Thomas BOESCH , Giuseppe DESOLI
CPC classification number: G06F17/15 , G06F7/5443
Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry. The convolutional accelerator, in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry, in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.
-
公开(公告)号：US20230418559A1
公开(公告)日：2023-12-28
申请号：US17847817
申请日：2022-06-23
Inventor： Michele ROSSI , Thomas BOESCH , Giuseppe DESOLI
Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.
-
公开(公告)号：US20210081773A1
公开(公告)日：2021-03-18
申请号：US17023144
申请日：2020-09-16
Inventor： Nitin CHAWLA , Giuseppe DESOLI , Manuj AYODHYAWASI , Thomas BOESCH , Surinder Pal SINGH
IPC: G06N3/063 , G06F1/08 , G06F1/324 , G06F9/50 , G06N3/08 , G06F1/3228 , G06F1/3296
Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.
-
-
-
-
-
-
-
-
-
Search Results
41
records
(took 0.017 seconds)
