公开(公告)号：US20130057334A1

公开(公告)日：2013-03-07

申请号：US13669259

申请日：2012-11-05

Applicant: STMicroelectronics SA ,  ST Ericsson SA

Inventor： Frederic Hasbani ,  Pascal Urard ,  Fabrice Blisson ,  David Jacquet

IPC: H03K3/00

CPC classification number: H03K19/0016 ,  H03K19/0013 ,  H03K2217/0018

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract translation: 本公开中描述的实施例涉及一种用于为集成系统提供电力的方法，包括以下动作：向系统提供电源，接地和体偏置电压，体偏置电压包括p沟道MOS晶体管的体偏置电压， 大于或低于电源电压，以及n沟道MOS晶体管的体偏置电压低于或大于接地电压，根据系统的处理单元是否由系统提供的电压进行选择 在活动或不活动的时段期间，提供用于偏置处理单元的MOS晶体管的主体的电压，以及为处理单元的MOS晶体管的主体提供所选择的电压。

公开(公告)号：US10153754B2

公开(公告)日：2018-12-11

申请号：US15460520

申请日：2017-03-16

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Alok Kumar Tripathi ,  Amit Verma ,  Pascal Urard

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/00 ,  H03K3/3562

Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.

公开(公告)号：US08890728B2

公开(公告)日：2014-11-18

申请号：US14179993

申请日：2014-02-13

Applicant: STMicroelectronics SA

Inventor： Nicolas Le Dortz ,  Thierry Simon ,  Pascal Urard ,  Caroline Lelandais-Perrault

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

Abstract: According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M−1 trains involves respectively M−1 second signals gleaned from the derived signal and the suite of M−1 shift coefficients.

Abstract translation: 根据一种实施方式，一种方法包括估计，其一方面包括涉及采样信号的至少一部分的相关处理，从代表时间导数的导出信号中收集的至少一个第一信号的至少一部分 的采样信号和N个部分滤波信号的至少一部分，分别代表在采样信号侧翼的N对包围版本之间的N个加权差，N大于或等于1.另一方面，估计包括矩阵 对该相关处理的结果进行处理。 M-1列车的校正处理涉及从派生信号和一组M-1移位系数收集的M-1个第二信号。