公开(公告)号：US20160307899A1

公开(公告)日：2016-10-20

申请号：US15197509

申请日：2016-06-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US20150097212A1

公开(公告)日：2015-04-09

申请号：US14048232

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Pierre MORIN ,  Qing LIU ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823807 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7842

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

Abstract translation: 一种用于形成半导体器件的方法包括在应力半导体绝缘体晶片的应力半导体层上形成掩模层。 形成包围应力半导体层的隔离沟槽。 隔离沟槽延伸穿过掩模层并穿过SOI晶片的氧化物层。 绝缘体形成在隔离沟槽中。 在电介质体和应力半导体层的相邻侧壁上形成松弛减小衬垫。 应力半导体层上的掩模层被去除。

公开(公告)号：US20230352586A1

公开(公告)日：2023-11-02

申请号：US18146962

申请日：2022-12-27

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20210036156A1

公开(公告)日：2021-02-04

申请号：US17074121

申请日：2020-10-19

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20190304845A1

公开(公告)日：2019-10-03

申请号：US16445778

申请日：2019-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN ,  Yann MIGNOT

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L21/762 ,  H01L29/417 ,  H01L21/02 ,  H01L29/165 ,  H01L27/092

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20170221903A1

公开(公告)日：2017-08-03

申请号：US15489360

申请日：2017-04-17

Applicant: STMicroelectronics, Inc.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10879 ,  H01L21/2251 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78603 ,  H01L29/78654

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

公开(公告)号：US20210057414A1

公开(公告)日：2021-02-25

申请号：US17093528

申请日：2020-11-09

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US20200020808A1

公开(公告)日：2020-01-16

申请号：US16584647

申请日：2019-09-26

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20180315666A1

公开(公告)日：2018-11-01

申请号：US16027707

申请日：2018-07-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN ,  Yann MIGNOT

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L21/02 ,  H01L29/165 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20180069121A1

公开(公告)日：2018-03-08

申请号：US15798976

申请日：2017-10-31

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/15 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.