公开(公告)号：US20230387803A1

公开(公告)日：2023-11-30

申请号：US18359548

申请日：2023-07-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau

IPC: H02M3/158

CPC classification number: H02M3/158

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

公开(公告)号：US11750096B2

公开(公告)日：2023-09-05

申请号：US17388553

申请日：2021-07-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau

IPC: H02M3/158

CPC classification number: H02M3/158

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

公开(公告)号：US20200220462A1

公开(公告)日：2020-07-09

申请号：US16819721

申请日：2020-03-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau ,  Francois Amiard

IPC: H02M3/158 ,  H02M3/155 ,  H02M1/08

Abstract: A method includes switching a switching circuit of the switched-mode power supply in a synchronous mode by turning on and off switches of the switching circuit in synchrony with a clock signal, wherein the switching circuit is coupled to an inductive element, and wherein the synchronous mode comprises a charging phase and a discharging phase; switching the switching circuit in an asynchronous mode by turning on and off switches of the switching circuit without being synchronized with the clock signal, wherein the asynchronous mode comprises a charging phase and a discharging phase; charging the inductive element during the charging phase of the synchronous mode; discharging the inductive element during the discharging phase of the synchronous mode; charging the inductive element during the charging phase of the asynchronous mode; and discharging the inductive element during the discharging phase of the asynchronous mode.

公开(公告)号：US20190007038A1

公开(公告)日：2019-01-03

申请号：US15946506

申请日：2018-04-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  David Chesneau

IPC: H03K5/24 ,  H03K19/20 ,  H03F3/19

CPC classification number: H03K5/24 ,  H03F3/19 ,  H03K3/02337 ,  H03K5/1252 ,  H03K19/20 ,  H03K2005/00019

Abstract: A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A comparator is coupled between the input interface and the output interface. An amplifier is coupled between the input interface and the comparator. A neutralization circuit is configured to neutralize any change of state of the output signal starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation that compensates for a duration of propagation of signals within the amplifier.

公开(公告)号：US11575306B2

公开(公告)日：2023-02-07

申请号：US17242955

申请日：2021-04-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau ,  Francois Amiard ,  Helene Esch

IPC: H02M1/08 ,  H02M3/157 ,  H02M1/00

Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.

公开(公告)号：US20220038005A1

公开(公告)日：2022-02-03

申请号：US17388591

申请日：2021-07-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau

IPC: H02M3/158

Abstract: An embodiment voltage converter includes a first transistor and a second transistor coupled in series, and a first circuit configured to control the first and second transistors. The control terminal of the second transistor is coupled to a first output of the first circuit by a second circuit configured to delay the control signals supplied at the first output by a first duration. The control terminal of the first transistor is coupled to a second output of the first circuit by a circuit configured to delay the control signals supplied at the second output, for a second period of each operating cycle, by a duration equal to twice the first duration and, during a second period of each operating cycle, by a duration equal to the first duration.

公开(公告)号：US11171565B2

公开(公告)日：2021-11-09

申请号：US16584147

申请日：2019-09-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau ,  Helene Esch ,  Francois Amiard

IPC: H02M3/158 ,  H03F1/02

Abstract: In an embodiment, A device includes an operational amplifier and a feedback loop. The feedback loop is coupled between a first input of the operational amplifier and an output of the operational amplifier. The feedback loop is controllable according to a saturation of the operational amplifier. In one example, the device is incorporated in a microcontroller.

公开(公告)号：US20210249954A1

公开(公告)日：2021-08-12

申请号：US17242955

申请日：2021-04-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau ,  Francois Amiard ,  Helene Esch

IPC: H02M3/157 ,  H02M1/08 ,  H02M1/00

Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.

公开(公告)号：US20210184580A1

公开(公告)日：2021-06-17

申请号：US17183721

申请日：2021-02-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau

IPC: H02M3/158

Abstract: In an embodiment, a method for operating a voltage step-down switched mode power supply includes delivering an output voltage with an output stage having a power transistor that is cyclically made conducting by a first control signal. In PWM mode, the method includes generating an error voltage based on the output voltage and a reference voltage, and applying a first delay on a first control signal. The first delay is determined so as to reduce a difference between the error voltage and the reference voltage.

公开(公告)号：US20210126536A1

公开(公告)日：2021-04-29

申请号：US17078317

申请日：2020-10-23

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Helene Esch ,  David Chesneau

IPC: H02M3/158 ,  H02M3/335 ,  G05F3/24 ,  G05F1/56 ,  H03K17/082 ,  H03K17/687 ,  H03K19/00

Abstract: In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.