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Patent Agency Ranking
公开(公告)号：US20200313880A1
公开(公告)日：2020-10-01
申请号：US16824242
申请日：2020-03-19
Inventor： Fabrice MARINET , Michael PEETERS
IPC: H04L9/08 , H04L9/14 , G06F9/4401
Abstract: An electronic device includes processing circuitry and one or more memories, including a non-volatile memory. Ephemeral cryptographic key generation circuitry, in operation, applies a function to code stored in the non-volatile memory, generating an ephemeral cryptographic key. Cryptographic circuitry coupled between the processing circuitry and the one or more memories, in operation, performs one or more cryptographic operations on data using the generated ephemeral cryptographic key. The device may include a register, which, in operation, temporarily stores the generated ephemeral cryptographic key.
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公开(公告)号：US20200311247A1
公开(公告)日：2020-10-01
申请号：US16832966
申请日：2020-03-27
Inventor： Michael PEETERS , Fabrice MARINET
Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.
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公开(公告)号：US20200075611A1
公开(公告)日：2020-03-05
申请号：US16546002
申请日：2019-08-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pascal FORNARA , Fabrice MARINET
IPC: H01L27/112 , H01L23/58 , H01L23/528 , H01L23/522 , G11C17/18 , H01L23/525 , G11C17/16
Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
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公开(公告)号：US20200035624A1
公开(公告)日：2020-01-30
申请号：US16520458
申请日：2019-07-24
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Fabrice MARINET , Pascal FORNARA
IPC: H01L23/00 , H01L23/48 , H01L27/11521 , G11C16/10 , G11C16/14
Abstract: An attack on an integrated circuit using a beam of electrically charged particles is detected by collecting charges due to the attack using at least one electrically conductive body that is electrically coupled to the floating gate of a state transistor. Prior to the attack, the state transistor is configured to confer an initial threshold voltage. The collected charges passed to the floating gate cause a modification of the threshold voltage of the state transistor. Detection of the attack is made by determining that the threshold voltage of the state transistor is different from the initial threshold voltage.
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公开(公告)号：US20190220587A1
公开(公告)日：2019-07-18
申请号：US16249804
申请日：2019-01-16
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Fabrice MARINET
CPC classification number: G06F21/44 , B41J2/17546 , B41J2/17566 , G06F21/73 , G06F2221/2129
Abstract: A method of authenticating a first electronic circuit includes generating a first signature using the first electronic circuit, the generating of the first signature being based on states of a plurality of electric nodes distributed within the first electronic circuit. A second signature is generated using a second electronic circuit, the generating of the second signature being based on states of a plurality of electric nodes distributed within the second electronic circuit. The first signature is compared to the second signature. The first electronic circuit is authenticated based on the comparison of the first signature to the second signature.
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