公开(公告)号：US20200035623A1

公开(公告)日：2020-01-30

申请号：US16518755

申请日：2019-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00

Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.

公开(公告)号：US20210126000A1

公开(公告)日：2021-04-29

申请号：US17141498

申请日：2021-01-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L27/112 ,  H01L23/58 ,  H01L23/528 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L23/522

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

公开(公告)号：US20210019448A1

公开(公告)日：2021-01-21

申请号：US16928901

申请日：2020-07-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (ALPS) SAS

Inventor： Marc BENVENISTE ,  Fabien JOURNET ,  Fabrice MARINET

IPC: G06F21/75 ,  G06F21/44 ,  H04L9/32 ,  G06F1/08 ,  G06F3/12

Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.

公开(公告)号：US20230317637A1

公开(公告)日：2023-10-05

申请号：US18206923

申请日：2023-06-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00 ,  H01L29/788 ,  G06F21/75 ,  G06F21/79 ,  H01L23/522 ,  H10B41/35

CPC classification number: H01L23/573 ,  H01L29/7883 ,  H01L23/576 ,  G06F21/75 ,  G06F21/79 ,  H01L23/5223 ,  H10B41/35 ,  G06F21/87

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

公开(公告)号：US20210091015A1

公开(公告)日：2021-03-25

申请号：US17113645

申请日：2020-12-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00

Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.

公开(公告)号：US20250015016A1

公开(公告)日：2025-01-09

申请号：US18887429

申请日：2024-09-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00 ,  G06F21/75 ,  G06F21/79 ,  G06F21/87 ,  H01L23/522 ,  H01L29/788 ,  H10B41/35

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

公开(公告)号：US20240103873A1

公开(公告)日：2024-03-28

申请号：US18532946

申请日：2023-12-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  PROTON WORLD INTERNATIONAL N.V.

Inventor： Michael PEETERS ,  Fabrice MARINET

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30105

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

公开(公告)号：US20200310805A1

公开(公告)日：2020-10-01

申请号：US16833012

申请日：2020-03-27

Applicant: PROTON WORLD INTERNATIONAL N.V. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Michael PEETERS ,  Fabrice MARINET

IPC: G06F9/30 ,  G06F7/57

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

公开(公告)号：US20220244961A1

公开(公告)日：2022-08-04

申请号：US17721193

申请日：2022-04-14

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  PROTON WORLD INTERNATIONAL N.V.

Inventor： Michael PEETERS ,  Fabrice MARINET

IPC: G06F9/30

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

公开(公告)号：US20210028128A1

公开(公告)日：2021-01-28

申请号：US16932082

申请日：2020-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00 ,  H01L27/11524 ,  H01L29/788

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.