公开(公告)号：US09997236B1

公开(公告)日：2018-06-12

申请号：US15375390

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/418

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

公开(公告)号：US10283191B1

公开(公告)日：2019-05-07

申请号：US15917227

申请日：2018-03-09

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/00 ,  G11C11/412 ,  G11C7/14 ,  G11C11/419

Abstract: Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.

公开(公告)号：US10249363B2

公开(公告)日：2019-04-02

申请号：US16018610

申请日：2018-06-26

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C7/22 ,  G11C7/06 ,  G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16 ,  G11C7/10 ,  G11C8/16 ,  G11C11/413

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

公开(公告)号：US20190035454A1

公开(公告)日：2019-01-31

申请号：US16025647

申请日：2018-07-02

Applicant: STMicroelectronics International N.V.

Inventor： Dhori Kedar Janardan ,  Abhishek Pathak ,  Shishir Kumar

IPC: G11C11/417

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

公开(公告)号：US20180301186A1

公开(公告)日：2018-10-18

申请号：US16018610

申请日：2018-06-26

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C11/419 ,  G06F1/06 ,  G06F13/16 ,  G11C11/418

CPC classification number: G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.