公开(公告)号：US11521697B2

公开(公告)日：2022-12-06

申请号：US16742292

申请日：2020-01-14

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Abhishek Pathak

IPC: G11C29/38 ,  G11C29/44 ,  G11C8/10

Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

公开(公告)号：US20180166127A1

公开(公告)日：2018-06-14

申请号：US15375390

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/418

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

公开(公告)号：US09786364B1

公开(公告)日：2017-10-10

申请号：US15381501

申请日：2016-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/412 ,  G11C11/418

Abstract: Disclosed herein is an electronic device including a bit line and a complementary bit line, first and second cross coupled inverters, a first pass gate coupled between the complementary bit line and the first inverter, and a second pass gate coupled between the bit line and the second inverter. The electronic device also includes third and fourth cross coupled inverters, a third pass gate coupled between the complementary bit line and the third inverter, and a fourth pass gate coupled between the bit line and the fourth inverter. The first, second, and fourth inverters are powered between a supply node and a reference node, and the third inverter is powered between a floating node and the reference node. The first pass gate and third pass gate are coupled in parallel.

公开(公告)号：US10037794B1

公开(公告)日：2018-07-31

申请号：US15660371

申请日：2017-07-26

Applicant: STMicroelectronics International N.V.

Inventor： Dhori Kedar Janardan ,  Abhishek Pathak ,  Shishir Kumar

IPC: G11C5/06 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C7/227 ,  G11C11/419 ,  G11C2207/002

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

公开(公告)号：US20180166128A1

公开(公告)日：2018-06-14

申请号：US15375987

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16

CPC classification number: G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

公开(公告)号：US10706915B2

公开(公告)日：2020-07-07

申请号：US16351773

申请日：2019-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/00 ,  G11C11/412 ,  G11C7/14 ,  G11C11/419 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

公开(公告)号：US10418095B2

公开(公告)日：2019-09-17

申请号：US15978684

申请日：2018-05-14

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G11C7/04

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

公开(公告)号：US20180261278A1

公开(公告)日：2018-09-13

申请号：US15978684

申请日：2018-05-14

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/418

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

公开(公告)号：US10311944B2

公开(公告)日：2019-06-04

申请号：US16025647

申请日：2018-07-02

Applicant: STMicroelectronics International N.V.

Inventor： Dhori Kedar Janardan ,  Abhishek Pathak ,  Shishir Kumar

IPC: G11C5/06 ,  G11C11/417

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

公开(公告)号：US10032506B2

公开(公告)日：2018-07-24

申请号：US15375987

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C7/22 ,  G11C7/06 ,  G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16

CPC classification number: G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.