-
公开(公告)号：US20190266784A1
公开(公告)日：2019-08-29
申请号：US16280963
申请日：2019-02-20
Inventor： Surinder Pal SINGH , Thomas BOESCH , Giuseppe DESOLI
Abstract: Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes. The data volume sculpting unit is also arranged to identify a 3D volume within the 3D feature map that is dimensionally smaller than the 3D feature map and isolate data from the 3D feature map that is within the 3D volume for processing in a deep learning algorithm.
-
12.发明公开公开(公告)号：US20240354269A1
公开(公告)日：2024-10-24
申请号：US18304938
申请日：2023-04-21
Applicant: STMicroelectronics International N.V.
Inventor： Antonio DE VITA , Thomas BOESCH , Giuseppe DESOLI
IPC: G06F13/374 , G06F9/50
CPC classification number: G06F13/374 , G06F9/5077 , G06F2209/5011
Abstract: A stream switch includes a data router, configuration registers, and arbitration logic. The data router has a plurality of input ports, each having a plurality of associated virtual input channels, and a plurality of output ports, each having a plurality of associated virtual output channels. The data router transmits data streams from input ports to one or more output ports of the plurality of output ports. The configuration registers store configuration data associated with the virtual output channels of the respective output ports of the plurality of output ports. The stored configuration data identifies a source input port and virtual input channel ID associated with the virtual output channel of the output port. The arbitration logic allocates bandwidth of the data router based on request signals associated with virtual input channels of the input ports and the configuration data associated with the virtual output channels.
-
公开(公告)号：US20240330660A1
公开(公告)日：2024-10-03
申请号：US18426128
申请日：2024-01-29
Applicant: STMicroelectronics International N.V.
Inventor： Carmine CAPPETTA , Surinder Pal SINGH , Giuseppe DESOLI , Thomas BOESCH , Michele ROSSI
IPC: G06N3/0464 , G06N3/063
CPC classification number: G06N3/0464 , G06N3/063
Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.
-
公开(公告)号：US20240220278A1
公开(公告)日：2024-07-04
申请号：US18176323
申请日：2023-02-28
Inventor： Paolo Sergio ZAMBOTTI , Thomas BOESCH , Giuseppe DESOLI , Wolfgang Johann BETZ , David SIORPAES
IPC: G06F9/445
CPC classification number: G06F9/44505
Abstract: A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task. The configuration controller may retrieve the linked list from the memory via a high-speed data bus.
-
公开(公告)号：US20230004354A1
公开(公告)日：2023-01-05
申请号：US17940654
申请日：2022-09-08
Inventor： Nitin CHAWLA , Tanmoy ROY , Anuj GROVER , Giuseppe DESOLI
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
-
Patent Agency Ranking
公开(公告)号：US20210181828A1
公开(公告)日：2021-06-17
申请号：US17111373
申请日：2020-12-03
Inventor： Nitin CHAWLA , Anuj GROVER , Giuseppe DESOLI , Kedar Janardan DHORI , Thomas BOESCH , Promod KUMAR
IPC: G06F1/3234 , G11C11/413 , G05F3/24 , G06F1/3287 , G06F15/78
Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
-
公开(公告)号：US20200272779A1
公开(公告)日：2020-08-27
申请号：US15931445
申请日：2020-05-13
Inventor： Thomas BOESCH , Giuseppe DESOLI
Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.
-
公开(公告)号：US20190340314A1
公开(公告)日：2019-11-07
申请号：US16517371
申请日：2019-07-19
Inventor： Thomas BOESCH , Giuseppe DESOLI
Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.
-
公开(公告)号：US20180189424A1
公开(公告)日：2018-07-05
申请号：US15423292
申请日：2017-02-02
Inventor： Thomas BOESCH , Giuseppe DESOLI
Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.
-
20.发明公开公开(公告)号：US20240330677A1
公开(公告)日：2024-10-03
申请号：US18192589
申请日：2023-03-29
Applicant: STMicroelectronics International N.V.
Inventor： Carmine CAPPETTA , Paolo Sergio ZAMBOTTI , Thomas BOESCH , Giuseppe DESOLI
IPC: G06N3/08
CPC classification number: G06N3/08
Abstract: A neural network is able to reconfigure hardware accelerators on-the-fly without stopping downstream hardware accelerators. The neural network inserts a reconfiguration tag into the stream of feature data. If the reconfiguration tag matches an identification of a hardware accelerator, a reconfiguration process is initiated. Upstream hardware accelerators are paused while downstream hardware accelerators continue to operate. An epoch controller reconfigures the hardware accelerator via a bus. Normal operation of the neural network then resumes.
-
-
-
-
-
-
-
-
-
Search Results
42
records
(took 0.023 seconds)
