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公开(公告)号：US11340292B2
公开(公告)日：2022-05-24
申请号：US16506264
申请日：2019-07-09
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Venkata Narayanan Srinivasan , Srinivas Dhulipalla
IPC: G01R31/30 , G01R31/3173 , G01R31/317 , G01R31/319
Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.
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公开(公告)号：US20210011080A1
公开(公告)日：2021-01-14
申请号：US16506264
申请日：2019-07-09
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Venkata Narayanan Srinivasan , Srinivas Dhulipalla
IPC: G01R31/30 , G01R31/3173 , G01R31/317 , G01R31/319
Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.
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公开(公告)号：US10886931B1
公开(公告)日：2021-01-05
申请号：US16937955
申请日：2020-07-24
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Kavindu Shekhar Benjwal
Abstract: A circuit includes analog input nodes and switches selectively coupling each of the analog input nodes to a capacitive node. Each of the switches is controlled by a respective bit of a channel selection word. Level shifting circuits are respectively coupled in parallel with the switches. A sampling capacitor is coupled between an output node and ground, the output node being coupled to the capacitive node. An analog to digital converter operates to digitize voltages at the output node.
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Patent Agency Ranking
公开(公告)号：US20220350357A1
公开(公告)日：2022-11-03
申请号：US17242067
申请日：2021-04-27
Applicant: STMicroelectronics International N.V.
Inventor： Shashwat , Rajesh Narwal
Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.
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公开(公告)号：US10996266B2
公开(公告)日：2021-05-04
申请号：US16536462
申请日：2019-08-09
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Rajesh Narwal , Srinivas Dhulipalla
IPC: G01R31/28
Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.
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公开(公告)号：US20210041496A1
公开(公告)日：2021-02-11
申请号：US16536462
申请日：2019-08-09
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Rajesh Narwal , Srinivas Dhulipalla
IPC: G01R31/28
Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.
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公开(公告)号：US10771082B1
公开(公告)日：2020-09-08
申请号：US16560683
申请日：2019-09-04
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Kavindu Shekhar Benjwal
Abstract: An analog-to-digital converter includes a sampling capacitor connected to a multiplexer output, discharge circuitry discharging the sampling capacitor during a first period beginning at a start of a sampling cycle, and level shifting circuitry charging the sampling capacitor to a voltage at a first analog input node modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period beginning at expiration of the first period. A first switch connects the first analog input node to the output node to charge the sampling capacitor to the voltage at the first analog input node, at expiration of the second period, and disconnects the first analog input node from the output node at an end of the sampling cycle of the analog-to-digital converter.
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公开(公告)号：US20200014372A1
公开(公告)日：2020-01-09
申请号：US16027762
申请日：2018-07-05
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Pravesh Kumar Saini
Abstract: An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal.The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom.The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.
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