公开(公告)号：US08982651B2

公开(公告)日：2015-03-17

申请号：US13852222

申请日：2013-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/00 ,  G11C7/02 ,  G11C7/06

CPC classification number: G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C17/18

Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

Abstract translation: 存储器包括以行和列布置的活动存储单元的阵列，以及与活动存储器单元阵列相邻的至少一个虚拟存储单元列。 感测电路耦合到所述至少一个虚拟存储器单元列以感测与所述至少一个虚拟存储器单元列相关联的至少一个变化。 辅助电路耦合到有源存储器单元阵列。 辅助确定控制器耦合到感测电路以存储对应于与至少一个虚拟存储器单元列相关联的不同变化的输出辅助值的查找表，以基于查找表来确定来自查找表的输出辅助值 至少感测到的变化，并且基于所确定的输出辅助值来操作辅助电路。

公开(公告)号：US08724374B1

公开(公告)日：2014-05-13

申请号：US13655160

申请日：2012-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/00 ,  G11C5/14 ,  G11C11/41 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G11C7/00 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  G11C16/30

Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract translation: 存储单元包括真实数据节点，真实上拉晶体管，补码数据节点和补码上拉晶体管。 真正的开关电路选择性地将第一或第二电源电压提供给真正的上拉晶体管的源极。 真正的偏置开关电路选择性地将第三或第四电源电压提供给真正的上拉晶体管的主体。 当将逻辑高数据值写入真实数据存储节点时，控制电路使真正的开关电路提供第二电源电压和真偏压开关电路来提供第三电源电压。 第二电源电压高于第一电源电压，第四电源电压高于第三电源电压。 当向补码数据存储节点写入逻辑高数据值时，相对于补码上拉晶体管执行类似的操作。

公开(公告)号：US11798615B2

公开(公告)日：2023-10-24

申请号：US17721956

申请日：2022-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Tanmoy Roy

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C5/025 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

公开(公告)号：US10277207B1

公开(公告)日：2019-04-30

申请号：US15892308

申请日：2018-02-08

Applicant: STMicroelectronics International N.V.

Inventor： Alok Kumar Tripathi ,  Amit Verma ,  Anuj Grover ,  Deepak Kumar Bihani ,  Tanmoy Roy ,  Tanuj Agrawal

IPC: H03K3/00 ,  H03K3/3562 ,  G11C11/412

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

公开(公告)号：US20140293723A1

公开(公告)日：2014-10-02

申请号：US13852222

申请日：2013-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/06

CPC classification number: G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C17/18

Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

Abstract translation: 存储器包括以行和列布置的活动存储单元的阵列，以及与活动存储器单元阵列相邻的至少一个虚拟存储单元列。 感测电路耦合到所述至少一个虚拟存储器单元列以感测与所述至少一个虚拟存储器单元列相关联的至少一个变化。 辅助电路耦合到有源存储器单元阵列。 辅助确定控制器耦合到感测电路以存储对应于与至少一个虚拟存储器单元列相关联的不同变化的输出辅助值的查找表，以基于查找表来确定来自查找表的输出辅助值 至少感测到的变化，并且基于所确定的输出辅助值来操作辅助电路。

公开(公告)号：US12243584B2

公开(公告)日：2025-03-04

申请号：US18167580

申请日：2023-02-10

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Tanmoy Roy ,  Nitin Chawla

IPC: G11C11/41 ,  G11C11/419 ,  H10B10/00

Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.

公开(公告)号：US11605424B2

公开(公告)日：2023-03-14

申请号：US17375945

申请日：2021-07-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anuj Grover ,  Tanmoy Roy ,  Nitin Chawla

IPC: G11C11/41 ,  G11C11/419 ,  H01L27/11

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

公开(公告)号：US11335397B2

公开(公告)日：2022-05-17

申请号：US16994488

申请日：2020-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Tanmoy Roy

IPC: G11C16/04 ,  G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

公开(公告)号：US11776650B2

公开(公告)日：2023-10-03

申请号：US17846578

申请日：2022-06-22

Applicant: STMicroelectronics International N.V.

Inventor： Tanmoy Roy ,  Anuj Grover

IPC: G11C29/36 ,  G11C29/10 ,  G11C29/44

CPC classification number: G11C29/36 ,  G11C29/10 ,  G11C29/44 ,  G11C2029/3602 ,  G11C2207/2254

Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values. The stored data values may be stored in an in-memory compute cluster of the memory array, such that operations on the stored data values include combining the multiple data values of the in-memory compute cluster with at least a portion of the generated calibration information as at least part of an in-memory compute operation for the in-memory compute cluster.

公开(公告)号：US11257543B2

公开(公告)日：2022-02-22

申请号：US16894527

申请日：2020-06-05

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover

IPC: G11C13/00 ,  G06F9/50 ,  G06N3/063 ,  G11C29/00 ,  G11C29/26 ,  G11C29/44

Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.