公开(公告)号：US20140293723A1

公开(公告)日：2014-10-02

申请号：US13852222

申请日：2013-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/06

CPC classification number: G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C17/18

Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

Abstract translation: 存储器包括以行和列布置的活动存储单元的阵列，以及与活动存储器单元阵列相邻的至少一个虚拟存储单元列。 感测电路耦合到所述至少一个虚拟存储器单元列以感测与所述至少一个虚拟存储器单元列相关联的至少一个变化。 辅助电路耦合到有源存储器单元阵列。 辅助确定控制器耦合到感测电路以存储对应于与至少一个虚拟存储器单元列相关联的不同变化的输出辅助值的查找表，以基于查找表来确定来自查找表的输出辅助值 至少感测到的变化，并且基于所确定的输出辅助值来操作辅助电路。

公开(公告)号：US09524242B2

公开(公告)日：2016-12-20

申请号：US14166003

申请日：2014-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Harsh Rawat ,  Gangaikondan Subramani Visweswaran

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract translation: 缓存包括多个高速缓存路径，每个高速缓存路径具有标签存储器字段和对应的数据字段。 通过由读取存储器地址（读取标签部分和读取索引部分）和写入存储器地址（写入标签部分和写入索引部分）定义的同时读取操作，高速缓存确定读取高速缓存命中并从一种高速缓存读取 如读取的存储器地址的读取标签和索引部分所示。 此外，确定写入存储器地址的写入标签和索引部分所指示的写入是否将以与读取相同的一种高速缓存方式进行，以便被冲突。 如果存在这样的冲突，则写入将与读取到一个缓存方式同时实现到与用于读取的不同的缓存方式。

公开(公告)号：US20150212945A1

公开(公告)日：2015-07-30

申请号：US14166003

申请日：2014-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Harsh Rawat ,  Gangaikondan Subramani Visweswaran

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract translation: 缓存包括多个高速缓存路径，每个高速缓存路径具有标签存储器字段和对应的数据字段。 通过由读取存储器地址（读取标签部分和读取索引部分）和写入存储器地址（写入标签部分和写入索引部分）定义的同时读取操作，高速缓存确定读取高速缓存命中并从一种高速缓存读取 如读取的存储器地址的读取标签和索引部分所示。 此外，确定写入存储器地址的写入标签和索引部分所指示的写入是否将以与读取相同的一种高速缓存方式进行，以便被冲突。 如果存在这样的冲突，则写入将与读取到一个缓存方式同时实现到与用于读取的不同的缓存方式。

公开(公告)号：US20140112081A1

公开(公告)日：2014-04-24

申请号：US13655160

申请日：2012-10-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  G11C16/30

Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract translation: 存储单元包括真实数据节点，真实上拉晶体管，补码数据节点和补码上拉晶体管。 真正的开关电路选择性地将第一或第二电源电压提供给真正的上拉晶体管的源极。 真正的偏置开关电路选择性地将第三或第四电源电压提供给真正的上拉晶体管的主体。 当将逻辑高数据值写入真实数据存储节点时，控制电路使真正的开关电路提供第二电源电压和真偏压开关电路来提供第三电源电压。 第二电源电压高于第一电源电压，第四电源电压高于第三电源电压。 当向补码数据存储节点写入逻辑高数据值时，相对于补码上拉晶体管执行类似的操作。

公开(公告)号：US09305633B2

公开(公告)日：2016-04-05

申请号：US14283120

申请日：2014-05-20

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C11/00 ,  G11C11/412 ,  G11C5/02 ,  G11C11/415 ,  G11C11/413 ,  G11C11/419 ,  G11C11/416 ,  G11C11/411

CPC classification number: G11C11/412 ,  G11C5/02 ,  G11C8/16 ,  G11C11/4116 ,  G11C11/413 ,  G11C11/415 ,  G11C11/416 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104

Abstract: Embodiments include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts.

Abstract translation: 实施例包括SRAM单元阵列，SRAM单元及其形成方法。 一个实施例是包括多个重叠矩形区域的静态随机存取存储器（SRAM）单元阵列。 每个重叠矩形区域包括整个第一SRAM单元，矩形区域的第一角区域中的第二相邻SRAM单元的一部分和矩形区域的第二角区域中的第三相邻SRAM单元的一部分， 第二角区域与第一角区域相对。 实施例还包括多指细胞布局。

公开(公告)号：US20150302917A1

公开(公告)日：2015-10-22

申请号：US14283120

申请日：2014-05-20

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C11/412 ,  G11C5/02

CPC classification number: G11C11/412 ,  G11C5/02 ,  G11C8/16 ,  G11C11/4116 ,  G11C11/413 ,  G11C11/415 ,  G11C11/416 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104

Abstract: Embodiments of the present disclosure include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts.

Abstract translation: 本公开的实施例包括SRAM单元的阵列，SRAM单元及其形成方法。 一个实施例是包括多个重叠矩形区域的静态随机存取存储器（SRAM）单元阵列。 每个重叠矩形区域包括整个第一SRAM单元，矩形区域的第一角区域中的第二相邻SRAM单元的一部分和矩形区域的第二角区域中的第三相邻SRAM单元的一部分， 第二角区域与第一角区域相对。 实施例还包括多指细胞布局。

公开(公告)号：US09177637B1

公开(公告)日：2015-11-03

申请号：US14472166

申请日：2014-08-28

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/06

CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1048 ,  G11C2207/002

Abstract: A dual rail SRAM array includes a plurality of columns of memory cells each coupled between two bit lines. A sense amplifier is coupled between each pair of bit lines. Capacitors are positioned between the sense amplifier outputs and the bit lines, thereby separating the sense amplifier from the bit lines. The memory cells are powered with an array supply voltage. The sense amplifier is powered with a peripheral supply voltage. During a read operation of the memory array, the bit lines are precharged to the array supply voltage. The sense amplifier is precharged to the peripheral supply voltage or to an intermediate voltage.

Abstract translation: 双轨SRAM阵列包括多个存储单元列，每个存储单元分别耦合在两个位线之间。 读出放大器耦合在每对位线之间。 电容器位于感测放大器输出和位线之间，从而将读出放大器与位线分离。 存储单元由阵列电源电压供电。 读出放大器由周边电源供电。 在存储器阵列的读取操作期间，位线被预充电到阵列电源电压。 读出放大器被预充电到外围电源电压或中间电压。

公开(公告)号：US08982651B2

公开(公告)日：2015-03-17

申请号：US13852222

申请日：2013-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/00 ,  G11C7/02 ,  G11C7/06

CPC classification number: G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C17/18

Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

Abstract translation: 存储器包括以行和列布置的活动存储单元的阵列，以及与活动存储器单元阵列相邻的至少一个虚拟存储单元列。 感测电路耦合到所述至少一个虚拟存储器单元列以感测与所述至少一个虚拟存储器单元列相关联的至少一个变化。 辅助电路耦合到有源存储器单元阵列。 辅助确定控制器耦合到感测电路以存储对应于与至少一个虚拟存储器单元列相关联的不同变化的输出辅助值的查找表，以基于查找表来确定来自查找表的输出辅助值 至少感测到的变化，并且基于所确定的输出辅助值来操作辅助电路。

公开(公告)号：US08724374B1

公开(公告)日：2014-05-13

申请号：US13655160

申请日：2012-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/00 ,  G11C5/14 ,  G11C11/41 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G11C7/00 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  G11C16/30

Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract translation: 存储单元包括真实数据节点，真实上拉晶体管，补码数据节点和补码上拉晶体管。 真正的开关电路选择性地将第一或第二电源电压提供给真正的上拉晶体管的源极。 真正的偏置开关电路选择性地将第三或第四电源电压提供给真正的上拉晶体管的主体。 当将逻辑高数据值写入真实数据存储节点时，控制电路使真正的开关电路提供第二电源电压和真偏压开关电路来提供第三电源电压。 第二电源电压高于第一电源电压，第四电源电压高于第三电源电压。 当向补码数据存储节点写入逻辑高数据值时，相对于补码上拉晶体管执行类似的操作。