公开(公告)号：US20030018861A1

公开(公告)日：2003-01-23

申请号：US10159782

申请日：2002-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Massimiliano Picca ,  Roberto Ravasio ,  Stefano Zanardi

IPC: G06F012/00

CPC classification number: G06F11/1072 ,  G11C2211/5641

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

Abstract translation: 一种用于存储可配置位数的多电平存储单元中的误差控制的方法。 使用在编码阶段中对由r位数据的k个符号组成的b位二进制字符串进行操作的错误控制代码执行错误控制。 当存储器单元存储数位r的位时，仅与存储在存储单元中的数据位形成数据符号。 当存储器单元存储少于r的位数时，形成数据符号，其中存储在存储单元中的数据位和具有预定逻辑值的rs位，其中存储在存储单元中的数据位 被布置在数据符号的最低有效部分中，并且具有预定逻辑值的rs位被布置在数据符号的最重要部分中。

公开(公告)号：US20020191444A1

公开(公告)日：2002-12-19

申请号：US10119523

申请日：2002-04-09

Applicant: STMicroelectronics S.r.I.

Inventor： Stefano Gregori ,  Rino Micheloni ,  Andrea Pierin ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

Abstract translation: 用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量 第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。 编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于 第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。

公开(公告)号：US20020089317A1

公开(公告)日：2002-07-11

申请号：US10008540

申请日：2001-11-07

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Ilaria Motta ,  Rino Micheloni ,  Guido Torelli

IPC: G05F001/40

CPC classification number: G05F1/56

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

Abstract translation: 一种电压调节器，具有比较器，输出端子是调节器的输出端子，用于连接到电压源的端子，连接到比较器的输入端子的参考电压源，以及连接在输出端子之间的反馈电路 和比较器的另一个输入端。 为了防止从待机状态转换到活动状态的瞬变，提供了提供基本上等于第一源的参考电压的第二参考电压源，用于将第二源连接到另一个输入端的开关 的控制电路，以及控制电路，其能够启动调节器的供应并且可以在调节器的供应被激活时将开关闭合预定的一段时间。

公开(公告)号：US20020054504A1

公开(公告)日：2002-05-09

申请号：US09957628

申请日：2001-09-19

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C016/04

CPC classification number: G11C11/5621 ,  G11C16/0416 ,  G11C2211/5641

Abstract: The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel array is used for storing high-density data, for which speed of reading is not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device, can be common to both arrays.

Abstract translation: 多电平存储器件具有存储器部分，该存储器部分包含可以以大于2的预定数量的级别（即，多级阵列）编程的单元，以及包含可以用两个级别编程的单元的存储器部分，即双层阵列。 多级阵列用于存储高密度数据，读取速度不是必需的，例如用于存储包括存储器件的系统的操作代码。 另一方面，双层阵列用于存储读取的高速度和可靠性至关重要的数据，例如个人计算机的BIOS以及要存储在高速缓冲存储器中的数据。 专用于编程，写入测试指令的电路部分以及存储器件操作所需的所有功能对于这两个阵列都是共同的。