公开(公告)号：US20020048187A1

公开(公告)日：2002-04-25

申请号：US09972726

申请日：2001-10-04

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Pierin ,  Stefano Gregori ,  Rino Micheloni ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C7/06 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26

Abstract: A multilevel nonvolatile memory includes a supply line supplying a supply voltage, a voltage boosting circuit supplying a boosted voltage, higher than the supply voltage, a boosted line connected to the voltage boosting circuit and a reading circuit including at least one comparator. The comparator includes a first and a second input, a first and a second output, at least one amplification stage connected to the boosted line, and a boosted line latch stage connected to the supply line.

Abstract translation: 多级非易失性存储器包括提供电源电压的电源线，提供高于电源电压的升压电压的升压电路，连接到升压电路的升压线路和包括至少一个比较器的读取电路。 比较器包括第一和第二输入，第一和第二输出，连接到升压线路的至少一个放大级和连接到电源线的升压线路锁存级。

公开(公告)号：US20020191444A1

公开(公告)日：2002-12-19

申请号：US10119523

申请日：2002-04-09

Applicant: STMicroelectronics S.r.I.

Inventor： Stefano Gregori ,  Rino Micheloni ,  Andrea Pierin ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

Abstract translation: 用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量 第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。 编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于 第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。

公开(公告)号：US20020089317A1

公开(公告)日：2002-07-11

申请号：US10008540

申请日：2001-11-07

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Ilaria Motta ,  Rino Micheloni ,  Guido Torelli

IPC: G05F001/40

CPC classification number: G05F1/56

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

Abstract translation: 一种电压调节器，具有比较器，输出端子是调节器的输出端子，用于连接到电压源的端子，连接到比较器的输入端子的参考电压源，以及连接在输出端子之间的反馈电路 和比较器的另一个输入端。 为了防止从待机状态转换到活动状态的瞬变，提供了提供基本上等于第一源的参考电压的第二参考电压源，用于将第二源连接到另一个输入端的开关 的控制电路，以及控制电路，其能够启动调节器的供应并且可以在调节器的供应被激活时将开关闭合预定的一段时间。

公开(公告)号：US20020057604A1

公开(公告)日：2002-05-16

申请号：US09953070

申请日：2001-09-13

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Alessandro Manstretta ,  Guido Torelli

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C16/28 ,  G11C2207/063

Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving at the input thereof a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, as well as at least one differential amplifier, connected at the input of the first and the second nodes and having an output terminal effective to provide a logic signal correlated to the selected cell information. The reading circuit also includes at least a first voltage-controlled discharge switch circuit connected at the input of the first node and to a voltage reference, a second voltage-controlled discharge switch circuit connected at the input of the second node and to the voltage reference, as well as a first and a second voltage comparator circuits receiving at the input thereof the first selected cell voltage and the second reference cell voltage. Moreover, advantageously according to the invention, the comparator circuits are effective to control the switch circuits.

Abstract translation: 一种用于连接到至少一个选定单元和至少一个参考单元的半导体非易失性存储器的读取电路，所述电路包括电流/电压转换电路，其在输入端接收流过选定单元的第一电流和流过所选单元的第二电流 所述参考单元并且分别在第一电路节点上提供第一选择的单元电压，并在第二节点上提供第二参考单元电压以及至少一个差分放大器，所述差分放大器连接在所述第一和第二节点的输入端，并且具有 输出端有效地提供与所选择的单元信息相关的逻辑信号。 读取电路还包括至少连接在第一节点的输入端和电压基准的第一压控放电开关电路，连接在第二节点的输入端的第二压控放电开关电路和电压基准 以及在其输入端接收第一选定单元电压和第二参考单元电压的第一和第二电压比较器电路。 此外，有利地根据本发明，比较器电路有效地控制开关电路。