公开(公告)号：US20020048187A1

公开(公告)日：2002-04-25

申请号：US09972726

申请日：2001-10-04

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Pierin ,  Stefano Gregori ,  Rino Micheloni ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C7/06 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26

Abstract: A multilevel nonvolatile memory includes a supply line supplying a supply voltage, a voltage boosting circuit supplying a boosted voltage, higher than the supply voltage, a boosted line connected to the voltage boosting circuit and a reading circuit including at least one comparator. The comparator includes a first and a second input, a first and a second output, at least one amplification stage connected to the boosted line, and a boosted line latch stage connected to the supply line.

Abstract translation: 多级非易失性存储器包括提供电源电压的电源线，提供高于电源电压的升压电压的升压电路，连接到升压电路的升压线路和包括至少一个比较器的读取电路。 比较器包括第一和第二输入，第一和第二输出，连接到升压线路的至少一个放大级和连接到电源线的升压线路锁存级。

公开(公告)号：US20020191444A1

公开(公告)日：2002-12-19

申请号：US10119523

申请日：2002-04-09

Applicant: STMicroelectronics S.r.I.

Inventor： Stefano Gregori ,  Rino Micheloni ,  Andrea Pierin ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

Abstract translation: 用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量 第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。 编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于 第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。