公开(公告)号：US09978429B2

公开(公告)日：2018-05-22

申请号：US15477695

申请日：2017-04-03

Applicant: STMicroelectronics S.r.l

Inventor： Fabio Enrico Carlo Disegni ,  Giuseppe Castagna ,  Maurizio Francesco Perroni

IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.

公开(公告)号：US20170117051A1

公开(公告)日：2017-04-27

申请号：US15212208

申请日：2016-07-16

Applicant: STMicroelectronics S.r.l

Inventor： Fabio Enrico Carlo Disegni ,  Giuseppe Castagna ,  Maurizio Francesco Perroni

IPC: G11C16/30 ,  G11C16/08

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.

公开(公告)号：US09613712B1

公开(公告)日：2017-04-04

申请号：US15212208

申请日：2016-07-16

Applicant: STMicroelectronics S.r.l

Inventor： Fabio Enrico Carlo Disegni ,  Giuseppe Castagna ,  Maurizio Francesco Perroni

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/06 ,  G11C8/10

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.