公开(公告)号：US20180130788A1

公开(公告)日：2018-05-10

申请号：US15862924

申请日：2018-01-05

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat ,  Jean Jimenez

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/74 ,  H01L29/744

CPC classification number: H01L27/0251 ,  H01L27/0262 ,  H01L29/1095 ,  H01L29/7436 ,  H01L29/744

Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.

公开(公告)号：US20140197448A1

公开(公告)日：2014-07-17

申请号：US14155891

申请日：2014-01-15

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H01L27/02 ,  H01L21/8249

CPC classification number: H01L21/8249 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/747 ,  H01L29/87

Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.

Abstract translation: 在给定的CMOS技术中在体半导体衬底上制造集成电路，并且包括用于防止静电放电的半导体器件。 半导体器件具有并联和头对尾耦合的双栅极晶闸管。 每个晶闸管都有一对电极区域。 两个晶闸管分别具有两个单独的栅极和公共半导体栅极区域。 每个晶闸管的两个晶体管的电流增益的乘积大于1.至少一个晶闸管的每个电极区域具有垂直于相应对的两个电极的间隔方向测量的尺寸，该尺寸被调整 以便使可控硅的本征触发电压小于要保护的晶体管的击穿电压，并且在CMOS技术中产生。

公开(公告)号：US08598938B2

公开(公告)日：2013-12-03

申请号：US13666727

申请日：2012-11-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H03K17/687

CPC classification number: H03K17/063 ,  H01L27/0262

Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.

Abstract translation: 电源开关包括在第一和第二节点之间串联的第一和第二MOS晶体管。 第一和第二晶体管都具有耦合到其衬底的栅极。 第一和第二电阻元件分别耦合在第一晶体管的栅极和第一节点之间，以及第二晶体管的栅极和第二节点之间。 三端双向可控硅开关元件耦合在第一和第二节点之间。 三端双向可控硅开关元件的栅极耦合到第一和第二晶体管共同的第三节点。 第三MOS晶体管具有耦合到第一晶体管的栅极的第一导电电极和耦合到第二晶体管的栅极的第二导电电极。

公开(公告)号：US20180254270A1

公开(公告)日：2018-09-06

申请号：US15694403

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat

IPC: H01L27/02 ,  H01L27/06 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L27/0277 ,  H01L27/0629 ,  H01L28/20 ,  H02H9/046

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

公开(公告)号：US09991173B2

公开(公告)日：2018-06-05

申请号：US14155891

申请日：2014-01-15

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H01L21/8249 ,  H01L29/747 ,  H01L27/02 ,  H01L29/87 ,  H01L29/06

CPC classification number: H01L21/8249 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/747 ,  H01L29/87

Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate, thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.

公开(公告)号：US09614367B2

公开(公告)日：2017-04-04

申请号：US14475683

申请日：2014-09-03

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02 ,  H01L29/74

CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L27/0277 ,  H01L29/7436 ,  H02H9/044

Abstract: A device includes a transistor configured for operating in a hybrid mode, an element configured for generating and injecting a current into the substrate of the transistor in the presence of an ESD pulse, and a thyristor triggerable at least by the element.

公开(公告)号：US20160380427A1

公开(公告)日：2016-12-29

申请号：US14964704

申请日：2015-12-10

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat ,  Boris Heitz ,  Jean Jimenez

IPC: H02H9/04

CPC classification number: H02H9/04 ,  H01L27/0262 ,  H01L27/0285 ,  H02H9/046

Abstract: An electronic device includes first and second terminals with an electronic circuit coupled there between. The electronic circuit includes a protection circuit and a resistive-capacitive circuit. The resistive-capacitive circuit triggers the protection circuit to protect against electrostatic discharges in the presence of a current pulse between the first and second terminals. A control circuit is configured to slow down a discharge from the resistive-capacitive circuit when the protection circuit is triggered.

Abstract translation: 电子设备包括第一和第二终端，其间连接有电子电路。 电子电路包括保护电路和电阻电容电路。 电阻电容电路在第一和第二端子之间存在电流脉冲的情况下触发保护电路以防止静电放电。 控制电路被配置为当触发保护电路时减缓来自电阻电容电路的放电。

公开(公告)号：US20150077888A1

公开(公告)日：2015-03-19

申请号：US14475683

申请日：2014-09-03

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L27/0277 ,  H01L29/7436 ,  H02H9/044

Abstract: A device includes a transistor configured for operating in a hybrid mode, an element configured for generating and injecting a current into the substrate of the transistor in the presence of an ESD pulse, and a thyristor triggerable at least by the element.

Abstract translation: 一种器件包括被配置为以混合模式操作的晶体管，被配置为在存在ESD脉冲的情况下产生并注入到晶体管的衬底中的元件以及至少可被该元件触发的晶闸管。

公开(公告)号：US20130120049A1

公开(公告)日：2013-05-16

申请号：US13666727

申请日：2012-11-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H03K17/72

CPC classification number: H03K17/063 ,  H01L27/0262

Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.

Abstract translation: 电源开关包括在第一和第二节点之间串联的第一和第二MOS晶体管。 第一和第二晶体管都具有耦合到其衬底的栅极。 第一和第二电阻元件分别耦合在第一晶体管的栅极和第一节点之间，以及第二晶体管的栅极和第二节点之间。 三端双向可控硅开关元件耦合在第一和第二节点之间。 三端双向可控硅开关元件的栅极耦合到第一和第二晶体管共同的第三节点。 第三MOS晶体管具有耦合到第一晶体管的栅极的第一导电电极和耦合到第二晶体管的栅极的第二导电电极。