公开(公告)号：US08217457B1

公开(公告)日：2012-07-10

申请号：US12272042

申请日：2008-11-17

Applicant: Samit Sengupta ,  Cheng-Hsiung Huang ,  Wei-Guang Wu

Inventor： Samit Sengupta ,  Cheng-Hsiung Huang ,  Wei-Guang Wu

IPC: H01L23/62

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.

Abstract translation: 一方面，本发明包括一种静电放电（ESD）保护电路，其包括多个输入电路，其中每个输入电路包括串联连接在电源与地之间的第一PMOS和第一NMOS晶体管以及第一和第二反相器 连接到第一PMOS和NMOS晶体管的栅极。 连接到第一NMOS晶体管的栅极的每个反相器包括连接在该栅极和地之间的第二NMOS晶体管，并且第二NMOS晶体管的栅极宽度与第一NMOS晶体管的栅极宽度之比 输入电路基本相同。 在本发明的另一方面，多指栅极晶体管形成在一个导电类型的第一阱中，该第一阱由相同导电类型的第二阱围绕，该第二阱由浅沟槽隔离和一部分 基质。 第二个阱用作第一个阱的抽头，而衬底电流路径的电阻显着增加。 形成该结构的方法是本发明的另一方面。

公开(公告)号：US06413152B1

公开(公告)日：2002-07-02

申请号：US09470296

申请日：1999-12-22

Applicant: Samit Sengupta ,  Charles F. Drill

Inventor： Samit Sengupta ,  Charles F. Drill

IPC: B24B700

CPC classification number: B24B37/345 ,  B24B27/0076 ,  B24B37/30 ,  B24B47/12 ,  B24B55/06

Abstract: An apparatus for chemical-mechanical planarization (CMP) of semiconductor wafers that allows independent micro-control of each spindle for tailored CMP performance. The present invention provides, in one embodiment, a CMP tool that includes a stationary bridge that houses a rack and pinion assembly. The rack and pinion assembly is coupled to a plurality of motor assemblies each of which is coupled to rotate a spindle. Significantly, movements of the spindles across are individually and independently controlled by the rack and pinion assembly. An advantage of the present independent spindle motion design allows optimization of the CMP process for each spindle and enables more accurate prediction of the effect of translation on CMP performance. Independent rotation and downforce capability of the present invention provides additional flexibility in terms of tuning polish rates and uniformity. Another advantage of the present invention is that a more compact enclosure for wafer isolation can be achieved.

Abstract translation: 用于半导体晶片的化学机械平面化（CMP）的设备，其允许对每个主轴进行独立的微控制以达到定制的CMP性能。 本发明在一个实施例中提供了一种CMP工具，其包括容纳齿条和小齿轮组件的固定桥。 齿条和小齿轮组件联接到多个马达组件，每个马达组件联接以旋转主轴。 重要的是，跨过的主轴的运动由齿条和小齿轮组件单独和独立地控制。 本独立主轴运动设计的优点允许优化每个主轴的CMP工艺，并能更准确地预测转换对CMP性能的影响。 本发明的独立旋转和下压力能力在调谐抛光速率和均匀性方面提供了额外的灵活性。 本发明的另一个优点是可以实现用于晶片隔离的更紧凑的外壳。

公开(公告)号：US06255226B1

公开(公告)日：2001-07-03

申请号：US09201987

申请日：1998-12-01

Applicant: Tammy Zheng ,  Calvin Todd Gabriel ,  Samit Sengupta

Inventor： Tammy Zheng ,  Calvin Todd Gabriel ,  Samit Sengupta

IPC: H01L21302

CPC classification number: H01L21/32136 ,  H01L21/76883

Abstract: In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Abstract translation: 在具有侵蚀性设计规则的现代亚微米技术中，导电线与底层通孔的完全重叠并不总是可能的。 具有金属互连的半导体器件的制造方法减小或消除了通孔中金属的凹陷，特别是当通孔中的金属是铝或铝合金时。 通过操纵蚀刻化学，使得铝合金，周围的阻挡金属和电介质的蚀刻速率相当，可以在通孔的暴露部分中形成空隙而进行金属过蚀刻。 通过消除空隙，由于存在凹陷而导致的通孔变薄被最小化，并且电连接不易受电迁移的影响。 因此，器件产量和可靠性提高。

公开(公告)号：US06235609B1

公开(公告)日：2001-05-22

申请号：US09541768

申请日：2000-04-03

Applicant: Samit Sengupta ,  Faran Nouri

Inventor： Samit Sengupta ,  Faran Nouri

IPC: H01L2176

CPC classification number: H01L21/76232

Abstract: For use with a sub-micron semiconductor process, a trench isolation process enables the formation of a wider isolation oxide around the shallow trench isolation (STI) opening. The wider oxide width minimizes the recessing of oxide along the trench sidewalls during subsequent cleaning and etching steps. In a method for forming STI regions on a silicon substrate having a buffer oxide thereon and a nitride layer on top of the buffer oxide, a mask layer is defined on the nitride layer patterning isolation regions in unmasked areas of the nitride layer. Isolation regions of sufficient depth are etched through in unmasked areas of the nitride layer, the buffer oxide and into the silicon substrate. Performing a lateral etch (a nitride shaving) of the nitride layer under the mask layer undercuts a portion of the nitride layer under the mask layer. After the lateral etch, the mask layer is removed. The STI region is filled with an oxide layer and is planarized until the oxide layer is substantially flush with the nitride layer. The resulting oxide layer is wider and protects the STI region from subsequent processing.

Abstract translation: 为了与亚微米半导体工艺一起使用，沟槽隔离工艺使得能够在浅沟槽隔离（STI）开口周围形成更宽的隔离氧化物。 在随后的清洗和蚀刻步骤期间，较宽的氧化物宽度最小化沿着沟槽侧壁的氧化物的凹陷。 在其上具有缓冲氧化物的硅衬底上形成STI区域的方法和在缓冲氧化物顶部上的氮化物层的方法中，在氮化物层的未掩蔽区域上的图案化隔离区域上限定掩模层。 在氮化物层，缓冲氧化物和硅衬底的未掩模区域中蚀刻具有足够深度的隔离区域。 在掩模层下面进行氮化物层的横向蚀刻（氮化物刮削）使掩模层下面的氮化物层的一部分下切。 在横向蚀刻之后，去除掩模层。 STI区域填充有氧化物层并且被平坦化直到氧化物层与氮化物层基本上齐平。 所得到的氧化物层更宽并且保护STI区域免于后续处理。

公开(公告)号：US06228757B1

公开(公告)日：2001-05-08

申请号：US09035735

申请日：1998-03-05

Applicant: Samit Sengupta ,  Tammy Zheng

Inventor： Samit Sengupta ,  Tammy Zheng

IPC: H01L214763

CPC classification number: H01L21/76865 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76885

Abstract: A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The process includes forming a via in a device layer of the semiconductor device. A barrier layer is formed over the device layer and a metal layer is formed over the barrier layer. The metal layer also fills the via to form a via structure. A portion of the metal layer is then removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect the via structure adjacent the surface of the device layer. In particular, the spacer protects a portion of the via structure that does not overlap with the conductive structure.

Abstract translation: 具有金属互连的半导体器件的制造方法减小或消除了通孔中金属的凹陷，特别是当通孔中的金属是铝或铝合金时。 该方法包括在半导体器件的器件层中形成通孔。 在器件层上形成阻挡层，并且在阻挡层上形成金属层。 金属层还填充通孔以形成通孔结构。 然后去除金属层的一部分，并且金属层的剩余部分形成具有从阻挡层的表面延伸的侧壁的导电结构。 沿着导电结构的侧壁形成间隔物，并且使用间隔物去除阻挡层的一部分以保护邻近器件层表面的通孔结构。 特别地，间隔件保护与导电结构不重叠的通孔结构的一部分。