Abstract:
In a method of manufacturing a display substrate and a method of manufacturing a display panel, the display substrate includes a color filter layer disposed on a base substrate within a pixel area, a first organic insulating pattern disposed on a first boundary area between adjacent pixel areas, a pixel electrode disposed on the color filter layer, and a first blocking pattern disposed on the first organic insulating pattern. Accordingly, an organic insulating layer corresponding to the pixel area is removed so that deterioration of the display quality by impurities generated from the organic insulating layer may be minimized. In addition, a stepped portion of a blocking pattern disposed between a pixel area and a boundary area of a plurality of the pixel areas is reduced so that motion blurring of a liquid crystal may be prevented.
Abstract:
A liquid crystal display device that includes an array substrate, an opposite substrate and a liquid crystal display layer is described. The array substrate includes a pixel electrode and a lower alignment layer. The pixel electrode has a plurality of slit portions extending in different directions. The lower alignment layer includes a reactive mesogen (RM) diamine is formed on the pixel electrode to induce an alignment direction of the liquid crystal molecules. An upper alignment layer is formed on a common electrode of the opposite substrate. The RM is cured at surfaces of the lower and upper alignment layers in response to ultraviolet (UV) light, so that liquid crystal molecules have a pretilt angle. Therefore, the aperture ratio and the response time may be improved, and afterimages may be decreased, so that display quality may be improved.
Abstract:
A method for manufacturing a liquid crystal display (“LCD”) includes; disposing a gate line including a gate electrode on a substrate, disposing a gate insulating layer on the gate line, disposing a data layer including a data line, source electrode and a drain electrode facing the source electrode on the gate insulating layer, disposing a color filter on the gate insulating layer, disposing an overcoat layer on the color filter, disposing a planarization layer on a portion of the overcoat layer corresponding to the gate line, the data line and the drain electrode, and disposing a pixel electrode in contacted with the overcoat layer in a region corresponding to the color filter.
Abstract:
In a thin film transistor, first and second thin film transistors are connected to an Nth gate line and an Mth data line, and first and second sub pixel electrodes are connected to the first and second thin film transistors, respectively. A third thin film transistor includes a gate electrode connected to an (N+1)th gate line, a semiconductor layer overlapping with the gate electrode, a source electrode connected to the second sub pixel electrode and partially overlapping with the gate electrode, and a drain electrode facing the source electrode. A first auxiliary electrode is connected to the drain electrode and arranged on the same layer as the first and second sub pixel electrodes. An opposite electrode is arranged on the same layer as the gate line and at least partially overlaps with the first auxiliary electrode with at least one insulating layer disposed therebetween.