公开(公告)号：US20230215954A1

公开(公告)日：2023-07-06

申请号：US18176454

申请日：2023-02-28

Applicant: SAMSUNG DISPLAY CO., LTD

Inventor： YONG SU LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung Kim ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L29/78618 ,  H01L27/1288 ,  H01L27/124 ,  H01L29/7869 ,  H01L27/1225 ,  H01L29/78696 ,  H01L29/66969 ,  H01L29/41733 ,  H10K59/1213

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US20210074784A1

公开(公告)日：2021-03-11

申请号：US16953188

申请日：2020-11-19

Applicant: Samsung Display Co., Ltd.

Inventor： Sang Gab KIM ,  Hyunmin CHO ,  Taesung KIM ,  Subin BAE ,  Yu-Gwang JEONG ,  Jinseock KIM

IPC: H01L27/32 ,  H01L51/52 ,  H01L51/56

Abstract: A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.

公开(公告)号：US20200243638A1

公开(公告)日：2020-07-30

申请号：US16720230

申请日：2019-12-19

Applicant: Samsung Display Co., Ltd.

Inventor： Sukyoung YANG ,  Sangwoo SOHN ,  Dokeun SONG ,  Dongmin LEE ,  Sangwon SHIN ,  Hyuneok SHIN ,  Kyeong Su KO ,  Sang Gab KIM ,  Joongeol LEE

IPC: H01L27/32

Abstract: A conductive line for a display device may include a first layer including aluminum (Al) or an aluminum alloy, a second layer disposed on the first layer, the second layer including titanium nitride (TiNx), and a third layer disposed on the second layer, the third layer including titanium (Ti) and having a multilayer structure including a plurality of stacked sub-layers.

公开(公告)号：US20200168684A1

公开(公告)日：2020-05-28

申请号：US16681697

申请日：2019-11-12

Applicant: Samsung Display Co., Ltd.

Inventor： Sang Gab KIM ,  Hyunmin CHO ,  Taesung KIM ,  Subin BAE ,  Yu-Gwang JEONG ,  Jinseock KIM

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52

Abstract: A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.

公开(公告)号：US20190123065A1

公开(公告)日：2019-04-25

申请号：US16215520

申请日：2018-12-10

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang JEONG ,  Hyun Min CHO ,  Su Bin BAE ,  Shin II CHOI ,  Sang Gab KIM

IPC: H01L27/12 ,  H01L21/311 ,  H01L29/417

CPC classification number: H01L27/124 ,  G02F1/1368 ,  G02F2201/123 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/1218 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/78633

Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

公开(公告)号：US20170278867A1

公开(公告)日：2017-09-28

申请号：US15465154

申请日：2017-03-21

Applicant: Samsung Display Co. Ltd.

Inventor： Yu Gwang JEONG ,  Su Bin BAE ,  Hyun Min CHO ,  Sang Gab KIM

IPC: H01L27/12

Abstract: A display device may include a substrate, an active pattern layer, a gate insulating layer, a first metal pattern layer, an interlayer insulating layer, a second metal pattern layer, and a passivation film. The active pattern layer may be disposed on the substrate. The gate insulating layer may be disposed on the active pattern layer. The first metal pattern layer may be disposed on the gate insulating layer. The interlayer insulating layer may be disposed on the first metal pattern layer. The second metal pattern layer may be disposed on the interlayer insulating layer. The passivation film may be disposed on the side wall of the second metal pattern layer.

公开(公告)号：US20160380011A1

公开(公告)日：2016-12-29

申请号：US15262943

申请日：2016-09-12

Applicant: Samsung Display Co. Ltd.

Inventor： Ji Young PARK ,  Dong Il KIM ,  Sang Gab KIM

IPC: H01L27/12

CPC classification number: H01L27/1288 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L27/124

Abstract: A method of fabricating a display device includes forming a thin-film transistor including a gate electrode, a source electrode and a drain electrode on a substrate, forming a first insulating layer and a second insulating layer on the thin-film transistor, forming a common electrode on the second insulating layer by depositing a common electrode material on the second insulating layer, plasma-treating a photoresist pattern on the common electrode material, and etching the common electrode material using the plasma-treated photoresist pattern as a mask, defining a contact hole in the second insulating layer which corresponds to the drain electrode using the plasma-treated photoresist pattern and the common electrode as a mask, forming a third insulating layer on the second insulating layer and the common electrode to expose the contact hole and the drain electrode and forming a pixel electrode connected to the drain electrode on the third insulating layer.

公开(公告)号：US20160077377A1

公开(公告)日：2016-03-17

申请号：US14623728

申请日：2015-02-17

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Hun KIM ,  Moon Jung AN ,  Yun Jong YEO ,  Hyun Min CHO ,  Sang Gab KIM

IPC: G02F1/1335 ,  G02B5/30

CPC classification number: G02B5/3058 ,  G02F2001/133548

Abstract: Provided is a wire grid polarizer. The wire grid polarizer includes a substrate, and a plurality of conductive wire patterns which are in parallel with each other and projected from the substrate. The plurality of conductive wire patterns includes a conductive wire pattern material in which an oxide layer is defined at an outer side surface thereof, and an oxidation resistant layer on the oxide layer at the outer side surface of the conductive wire pattern material. The oxide layer is between the oxidation resistant layer and a remainder of the conductive wire pattern material.

Abstract translation: 提供了一种线栅偏振器。 线栅偏振器包括基板和彼此平行并从基板突出的多个导线图案。 多个导线图案包括在其外侧表面上限定氧化物层的导线图案材料和在导线图案材料的外侧表面处的氧化物层上的抗氧化层。 氧化层位于抗氧化层和导线图案材料的其余部分之间。

公开(公告)号：US20150194534A1

公开(公告)日：2015-07-09

申请号：US14666461

申请日：2015-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung KIM ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US20140124786A1

公开(公告)日：2014-05-08

申请号：US14151658

申请日：2014-01-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Pil Soon HONG ,  Gwui-Hyun PARK ,  Jin-Su BYUN ,  Sang Gab KIM

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L29/41733

Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

Abstract translation: 薄膜晶体管阵列面板及其制造方法技术领域本发明涉及一种薄膜晶体管阵列面板及其制造方法，其能够防止由于掩模的未对准而使布线断开，并且通过减少掩模数来简化处理并降低成本。 根据本发明的薄膜晶体管阵列面板包括：源电极，其包围第一接触孔的外部部分并形成在第二绝缘层上; 漏电极，其包围所述第二接触孔的外部部分并形成在所述第二绝缘层上; 第一连接电极，通过第一接触孔连接半导体层的源极区域和源极电极; 以及通过第二接触孔连接半导体层的漏极区域和漏极电极的第二连接电极。