Abstract:
A liquid crystal display device comprising: a substrate; a gate line that is disposed on the substrate and extends in a first direction; a first insulating film that is disposed on the gate line; a semiconductor pattern that is disposed on the first insulating film; a first transparent electrode that is disposed on the semiconductor pattern, and has a first electrode and a second electrode being spaced apart from each other; a second insulating film that is disposed on the first transparent electrode and partially exposes the first electrode; a data line disposed on the second insulating film and extends in a second direction different from the first direction; a second transparent electrode that is disposed on the second insulating film and at least partially overlaps the second electrode; and a connecting electrode in direct contact with a portion of the exposed first electrode and the data line.
Abstract:
A liquid crystal display includes a first substrate on which a plurality of gate lines and a plurality of data lines intersecting the gate lines are disposed, a second substrate facing the first substrate, a liquid crystal layer interposed between the first and second substrates, a linear electrode on the first substrate, a surface electrode on the first substrate, an insulating layer interposed between the linear electrode and the surface electrode, a thin film transistor electrically connected to the gate and data lines and electrically connected to the linear electrode, a black matrix disposed on any one of the first and second substrates and overlapping the gate and data lines, and a voltage storage electrode extending from one end portion of the linear electrode into the black matrix and overlapping the thin film transistor.
Abstract:
A liquid crystal display includes: a gate line including a gate electrode; a data line including a source electrode; a drain electrode; an organic layer on the gate and data lines and the drain electrode, and a first opening defined therein; a first electrode on the organic layer, and a second opening defined therein; and a passivation layer on the first electrode, and a contact hole defined therein exposing the drain electrode. An interval taken in a first direction between a first edge of the gate electrode, the first edge parallel to a second direction in which the gate line is extended and which is different than the first direction, and a second edge of the first electrode second opening, the second edge parallel to the second direction and adjacent to the gate electrode first edge is 0 micrometer to about 6 micrometers.
Abstract:
A thin film transistor array panel according to an exemplary embodiment of the invention includes: an insulating substrate; a gate line disposed on the insulating substrate and including a gate pad portion; a data line insulated from and crossing the gate line, and including a source electrode and a data pad portion; a drain electrode facing the source electrode; an organic insulating layer disposed on the data line and the drain electrode, and including a first contact hole; a common electrode disposed on the organic insulating layer, and including a second contact hole; a passivation layer disposed on the common electrode, and including a third contact hole; and a pixel electrode disposed on the passivation layer, and being in contact with the drain electrode, in which the third contact hole is disposed to be adjacent to one surface of the first contact hole for improvement of an aperture ratio and a stable electrode connection.
Abstract:
A liquid crystal display includes a plurality of pixels including first, second and third pixels that display different colors and are sequentially disposed, a plurality of data lines including first, second and third data lines sequentially and repeatedly disposed where the first data line is disposed between the third pixel and the first pixel, the second data line is disposed between the first pixel and the second pixel, and the third data line is disposed between the second pixel and the third pixel, widths of the first, second and third data lines are substantially the same as each other, and a first interval between the first data line and the second data line is different from a second interval between the second data line and the third data line or a third interval between the third data line and the first data line.
Abstract:
A liquid crystal display includes: a display area including: a first data line between a first pixel electrode and a second pixel electrode in a same pixel row, and connected to a first thin film transistor (“TFT”) and a second TFT, respectively; and a peripheral area including: a first parasitic capacitor capacity measuring unit including first gate capacity units and first data capacity units; a second parasitic capacitor capacity measuring unit including second gate capacity units and second data capacity units, where a relative arrangement between the first gate and data capacity units is the same as a relative arrangement between the gate and drain electrodes of the first TFT, and a relative arrangement between the second gate and data capacity units is the same as a relative arrangement between the gate and drain electrodes of the second TFT.
Abstract:
A display device includes a substrate, driving transistors, an insulating layer, and light emitting elements. The driving transistors are disposed in pixel areas on the substrate and each includes a first electrode and a second electrode. The insulating layer is disposed over the driving transistors to cover the first electrodes and the second electrodes of the driving transistors and has contact holes respectively overlapping with the first electrodes of the driving transistors. The light emitting elements are disposed on the insulating layer and include pixel electrodes respectively overlapping with the first electrodes of the driving transistors. In addition, an insulating pattern is disposed in at least one of the contact holes to prevent a corresponding pixel area from emitting light.
Abstract:
A thin film transistor array panel according to an exemplary embodiment of the invention includes: an insulating substrate; a gate line disposed on the insulating substrate and including a gate pad portion; a data line insulated from and crossing the gate line, and including a source electrode and a data pad portion; a drain electrode facing the source electrode; an organic insulating layer disposed on the data line and the drain electrode, and including a first contact hole; a common electrode disposed on the organic insulating layer, and including a second contact hole; a passivation layer disposed on the common electrode, and including a third contact hole; and a pixel electrode disposed on the passivation layer, and being in contact with the drain electrode, in which the third contact hole is disposed to be adjacent to one surface of the first contact hole for improvement of an aperture ratio and a stable electrode connection.
Abstract:
A thin film transistor array panel according to an exemplary embodiment of the invention includes: an insulating substrate; a gate line disposed on the insulating substrate and including a gate pad portion; a data line insulated from and crossing the gate line, and including a source electrode and a data pad portion; a drain electrode facing the source electrode; an organic insulating layer disposed on the data line and the drain electrode, and including a first contact hole; a common electrode disposed on the organic insulating layer, and including a second contact hole; a passivation layer disposed on the common electrode, and including a third contact hole; and a pixel electrode disposed on the passivation layer, and being in contact with the drain electrode, in which the third contact hole is disposed to be adjacent to one surface of the first contact hole for improvement of an aperture ratio and a stable electrode connection.
Abstract:
A liquid crystal display of an exemplary embodiment includes: first and second gate line disposed on a substrate and extending in a first direction; first and second data line disposed on the substrate; a first transistor connected to the first gate line and the first data line; a second transistor connected to the second gate line and the second data line; a first pixel electrode overlapping the first transistor and the first gate line; a second pixel electrode overlapping the second transistor and the second gate line; a reflective layer disposed between the first gate line and the first data line, the second data line and the first pixel electrode and extending in the first direction, the first pixel electrode is disposed at a next row of the second pixel electrode in the second direction, and the first transistor is connected to the second pixel electrode.