公开(公告)号：US09269726B2

公开(公告)日：2016-02-23

申请号：US14158133

申请日：2014-01-17

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min Park ,  Sung Kyun Park ,  Jung-Soo Lee ,  Ji-Hyun Kim ,  Jun Chun

IPC: H01L27/15 ,  H01L29/20 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1362

CPC classification number: H01L27/1248 ,  G02F1/134363 ,  G02F1/136227 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/78606 ,  H01L2021/775

Abstract: A thin film transistor (TFT) array panel and a manufacturing method thereof are disclosed. A contact hole may be formed to expose a pad disposed on a substrate of the TFT array panel. A first layer of a connecting member is formed with the same layer as a first field generating electrode and is disposed in the contact hole. A second passivation layer is disposed in the TFT array panel, but is removed at a region where the contact hole is formed and portions of the second passivation layer that cover the first layer of the connecting member. A second layer of the connecting member is formed on the first layer of the connecting member.

Abstract translation: 公开了薄膜晶体管（TFT）阵列面板及其制造方法。 可以形成接触孔以暴露设置在TFT阵列面板的基板上的焊盘。 连接构件的第一层形成有与第一场产生电极相同的层，并且设置在接触孔中。 第二钝化层设置在TFT阵列面板中，但是在形成接触孔的区域处被去除并且覆盖连接构件的第一层的第二钝化层的部分。 连接构件的第二层形成在连接构件的第一层上。

公开(公告)号：US09123873B2

公开(公告)日：2015-09-01

申请号：US14090487

申请日：2013-11-26

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min Park ,  Ji-Hyun Kim ,  Jung-Soo Lee ,  Sung Kyun Park

IPC: H01L31/112 ,  H01L33/58 ,  G02F1/1345 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/13458 ,  G02F1/136227 ,  G02F1/1368 ,  H01L27/1248 ,  H01L29/78669 ,  H01L29/78678 ,  H01L33/58

Abstract: Instead of forming contact holes the same way in both the non-image forming peripheral area (PA) and the image forming display area of a thin film transistor array panel, contact holes in the DA are formed to be substantially smaller than those in the PA for thereby improving an aperture ratio of the corresponding display device. In an exemplary embodiment, an inorganic gate insulating layer is not etched in the DA and only an inorganic first passivation layer among inorganic insulating layers positioned in the DA is etched to allow communication between the drain electrode and the corresponding field generating electrode. On the other hand, in the peripheral area, plural inorganic insulating layers such as the gate insulating layer, the first passivation layer, and the second passivation layer positioned on the gate wire and the data wire are simultaneously etched to form second contact holes and third contact holes exposing respective gate pads and data pads.

Abstract translation: 代替在非图像形成周边区域（PA）和薄膜晶体管阵列面板的图像形成显示区域中以相同的方式形成接触孔，DA中的接触孔形成为显着小于PA中的接触孔 从而提高对应的显示装置的开口率。 在一个示例性实施例中，在DA中不蚀刻无机栅极绝缘层，并且仅在位于DA中的无机绝缘层中只有无机第一钝化层被蚀刻以允许漏电极和相应的场产生电极之间的连通。 另一方面，在外围区域中，同时蚀刻位于栅极线上的多个无机绝缘层，例如栅极绝缘层，第一钝化层和第二钝化层以及数据线，形成第二接触孔，第三接触孔 接触孔暴露各个栅极焊盘和数据焊盘。

公开(公告)号：US10324568B2

公开(公告)日：2019-06-18

申请号：US15131359

申请日：2016-04-18

Applicant: Samsung Display Co., Ltd.

Inventor： Sang Youn Han ,  Kyung Seop Kim ,  Sung Kyun Park ,  Sang Kyu Choi

IPC: G06F3/045 ,  G06F3/044

Abstract: A touch panel includes a touch electrode disposed on a substrate, the touch electrode including a metal layer; a phase matching layer disposed on the metal layer; and a thin film layer disposed on the phase matching layer.

公开(公告)号：US09830031B2

公开(公告)日：2017-11-28

申请号：US14806864

申请日：2015-07-23

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Neung Kim ,  Jong Hyun Choi ,  Jeong-Hwan Kim ,  Won Baek Lee ,  Ki-Hyun Cho ,  Kyung Seop Kim ,  Cheol Kyu Kim ,  Sung Kyun Park ,  Sun Haeng Cho

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F2203/04103

Abstract: A touch screen panel includes a substrate, touch electrodes disposed on a touch area of the substrate and configured to sense a touch, and a connection line disposed on the touch area, the connection line including a first end connected a touch electrode of the touch electrodes and a second end connected to a pad, the pad including a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer, and a first protective conductive layer disposed on the second conductive layer, in which the touch electrode includes the first conductive layer, and the first protective conductive layer.

公开(公告)号：US09741748B2

公开(公告)日：2017-08-22

申请号：US14989319

申请日：2016-01-06

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min Park ,  Sung Kyun Park ,  Jung-Soo Lee ,  Ji-Hyun Kim ,  Jun Chun

IPC: H01L29/02 ,  G02F1/136 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1362 ,  H01L21/77

CPC classification number: H01L27/1248 ,  G02F1/134363 ,  G02F1/136227 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/78606 ,  H01L2021/775

Abstract: A thin film transistor array panel includes a substrate, a gate line and a gate pad disposed on the substrate, a gate insulating layer disposed on the gate line and the gate pad, a data line and a data pad disposed on the gate insulating layer, an organic layer disposed on the data line and the data pad, and a connecting member disposed on one of the gate pad and the data pad, in which the organic layer includes a first portion overlapping the connecting member and a second portion not overlapping the connecting member, and a height of the first portion of the organic layer is greater than a height of the second portion of the organic layer.

公开(公告)号：US09515096B2

公开(公告)日：2016-12-06

申请号：US14838055

申请日：2015-08-27

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min Park ,  Ji-Hyun Kim ,  Jung-Soo Lee ,  Sung Kyun Park

IPC: H01L27/12 ,  H01L33/58 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786

CPC classification number: H01L27/124 ,  G02F1/13458 ,  G02F1/136227 ,  G02F1/1368 ,  H01L27/1248 ,  H01L29/78669 ,  H01L29/78678 ,  H01L33/58

Abstract: The present disclosure provides a thin film transistor array. In an exemplary embodiment, the thin film transistor array includes: a substrate; a gate line including a gate pad and disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad; a data line including a data pad and disposed on the gate insulating layer; a first passivation layer disposed on the data line; a first electrode disposed on the first passivation layer; a second passivation layer disposed on the first electrode; and a second electrode disposed on the second passivation layer. The gate pad is exposed through a first contact hole, and the gate insulating layer, the first passivation layer, and the second passivation layer include at least a portion of the first contact hole.

Abstract translation: 本发明提供一种薄膜晶体管阵列。 在示例性实施例中，薄膜晶体管阵列包括：衬底; 栅极线，包括栅极焊盘并设置在所述衬底上; 设置在栅极线和栅极焊盘上的栅极绝缘层; 数据线，包括数据焊盘并设置在栅极绝缘层上; 设置在所述数据线上的第一钝化层; 设置在所述第一钝化层上的第一电极; 设置在所述第一电极上的第二钝化层; 以及设置在所述第二钝化层上的第二电极。 栅极焊盘通过第一接触孔露出，栅极绝缘层，第一钝化层和第二钝化层包括第一接触孔的至少一部分。

公开(公告)号：US20140183536A1

公开(公告)日：2014-07-03

申请号：US13915070

申请日：2013-06-11

Applicant: SAMSUNG DISPLAY, CO., LTD.

Inventor： Sung Kyun Park ,  Jeong Min Park ,  Jung-Soo Lee ,  Jin Ho Ju

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1259

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulation substrate; a thin film transistor disposed on the insulation substrate, wherein the thin film transistor includes a first electrode; a first contact hole pattern having a first width, wherein the first contact hole pattern exposes a portion of the first electrode, and a first contact hole to expose the portion of the first electrode, wherein an inner sidewall of the first contact hole pattern constitutes a first portion of the first contact hole.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：绝缘基板; 设置在所述绝缘基板上的薄膜晶体管，其中所述薄膜晶体管包括第一电极; 具有第一宽度的第一接触孔图案，其中所述第一接触孔图案暴露所述第一电极的一部分，以及第一接触孔，以暴露所述第一电极的所述部分，其中所述第一接触孔图案的内侧壁构成 第一接触孔的第一部分。