公开(公告)号：US10409593B2

公开(公告)日：2019-09-10

申请号：US15905979

申请日：2018-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F1/3287

Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

公开(公告)号：US10372451B2

公开(公告)日：2019-08-06

申请号：US15802844

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F9/38

Abstract: A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.

公开(公告)号：US20150019196A1

公开(公告)日：2015-01-15

申请号：US14376612

申请日：2013-01-30

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyun Woo Sim ,  Hyuk Min Kwon ,  Seung Wook Lee ,  Han Su Cho

IPC: G06F9/30 ,  G06F17/50

CPC classification number: G06F9/3001 ,  G06F9/30181 ,  G06F9/3889 ,  G06F9/3897 ,  G06F9/52 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5045 ,  G06F2217/68

Abstract: In order to achieve tasks, according to an embodiment of the present invention, an arithmetic unit including one or more ASIPs includes two or more processors, and an execution unit that is connected to the two or more processors and executes instructions received from the processors. According to an embodiment of the present invention, it is possible to provide a low-power, high-integration, high-performance arithmetic unit through resource sharing using the arithmetic unit including the one or more ASIPs, and it is possible to provide a method of designing an arithmetic unit that may be applied to a specific application.

Abstract translation: 为了实现任务，根据本发明的实施例，包括一个或多个ASIP的算术单元包括两个或更多个处理器，以及连接到两个或更多个处理器并执行从处理器接收的指令的执行单元。 根据本发明的实施例，可以通过使用包括一个或多个ASIP的算术单元通过资源共享来提供低功率，高集成度的高性能算术单元，并且可以提供一种方法 设计可应用于特定应用的算术单元。