公开(公告)号：US20170278580A1

公开(公告)日：2017-09-28

申请号：US15425557

申请日：2017-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BONGSOON LIM ,  SEOKMIN YOON ,  SANG-WON SHIM

IPC: G11C16/34 ,  G06F11/20 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G06F11/2094 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory device may include a cell array, a first page buffer, and a second page buffer. The first page buffer may be connected to a first memory cell of the cell array and may store first sensing data generated by sensing whether a program operation of the first memory cell is completed during a program verify operation. The second page buffer may be connected to a second memory cell of the cell array. During the program verify operation, the second page buffer may generate and store first verify data based on second sensing data generated by sensing whether a program operation of the second memory cell is completed, may receive the first sensing data from the first page buffer, and may store second verify data generated by accumulating the first sensing data and the first verify data.

公开(公告)号：US20220068403A1

公开(公告)日：2022-03-03

申请号：US17172288

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGWON SHIM ,  SANGWON PARK ,  BONGSOON LIM ,  YOONHEE CHOI

IPC: G11C16/30 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

公开(公告)号：US20210074716A1

公开(公告)日：2021-03-11

申请号：US16931500

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： BONGSOON LIM ,  DAESEOK BYEON

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11565 ,  G11C8/14 ,  G11C7/18 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11539 ,  H01L27/11556

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.