公开(公告)号：US20210142834A1

公开(公告)日：2021-05-13

申请号：US16909177

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408

Abstract: An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

公开(公告)号：US20210020227A1

公开(公告)日：2021-01-21

申请号：US16848418

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Buyeon Lee ,  Taegyeong Kim ,  Taesung Kim ,  Byongmo Moon

IPC: G11C11/4093 ,  H03K19/00 ,  G06F3/06

Abstract: A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.

公开(公告)号：US12210777B2

公开(公告)日：2025-01-28

申请号：US18242250

申请日：2023-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungmin Kim ,  Byongmo Moon

IPC: G06F3/06

Abstract: In some embodiments, a memory device includes a data sampler configured to sample a data signal based on a write data strobe signal, a measuring circuit configured to measure a temperature-based delay variation and a voltage-based delay variation of a transfer path of the write data strobe signal, a storage circuit configured to store a first coefficient code regulating a reference-based delay variation on the transfer path, a temperature sensor configured to sense the temperature of the transfer path, a monitoring circuit configured to generate a second coefficient code by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other, a reference voltage generator configured to generate a reference voltage, a voltage regulator configured to generate a regulation voltage, and a write data strobe signal transfer circuit configured to transfer the write data strobe signal to the data sampler.

公开(公告)号：US20230018451A1

公开(公告)日：2023-01-19

申请号：US17954860

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4074

Abstract: An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

公开(公告)号：US11356098B2

公开(公告)日：2022-06-07

申请号：US17353917

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo Moon ,  Jiyoung Kim ,  Seongook Jung ,  Jongsoo Lee

IPC: G11C7/10 ,  H03K19/173 ,  H03K19/0175 ,  G11C7/22 ,  H03K19/17788 ,  G11C7/14 ,  H03K19/017

Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

公开(公告)号：US11238921B2

公开(公告)日：2022-02-01

申请号：US16848418

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Buyeon Lee ,  Taegyeong Kim ,  Taesung Kim ,  Byongmo Moon

IPC: G11C11/4093 ,  G06F3/06 ,  H03K19/00

Abstract: A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.

公开(公告)号：US11189332B2

公开(公告)日：2021-11-30

申请号：US16842891

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewoo Jeong ,  Byongmo Moon

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C29/12 ,  G11C11/4091

Abstract: A memory device includes a memory cell array including a plurality of memory cells storing data, a sense amplifier connected to the memory cell array, and a voltage controller. The voltage controller includes a voltage driver that generates a control signal and an overdrive controller that generates an overdrive control signal that regulates the generating of the control signal in response to at least one of a result of a comparison between the control signal and a reference voltage, and process, voltage, temperature (PVT) information. The voltage driver adjusts the control signal in response to the overdrive control signal to generate an overdriven control signal and outputs the overdriven control signal to the sense amplifier.