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公开(公告)号：US11636894B2
公开(公告)日：2023-04-25
申请号：US17335509
申请日：2021-06-01
发明人： Heekyung Choi , Taemin Choi , Seongook Jung , Keonhee Cho
IPC分类号： G11C11/419 , G11C11/4096 , G11C11/408 , G11C5/06 , G11C11/4099 , G11C11/4094
摘要： An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.
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公开(公告)号：US20220115060A1
公开(公告)日：2022-04-14
申请号：US17478629
申请日：2021-09-17
发明人： Taemin Choi , Taehyun Kim , Seongook Jung
IPC分类号： G11C11/419 , G11C11/418
摘要： A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.
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公开(公告)号：US20240282367A1
公开(公告)日：2024-08-22
申请号：US18639330
申请日：2024-04-18
发明人： Taemin Choi , Taehyun Kim , Seongook Jung
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C11/418
摘要： A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.
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公开(公告)号：US20220130453A1
公开(公告)日：2022-04-28
申请号：US17332004
申请日：2021-05-27
发明人： Taemin Choi , Seongook Jung , Keonhee Cho
IPC分类号： G11C11/412 , G11C11/419 , G11C11/418
摘要： An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.
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公开(公告)号：US11990179B2
公开(公告)日：2024-05-21
申请号：US17478629
申请日：2021-09-17
发明人： Taemin Choi , Taehyun Kim , Seongook Jung
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C11/418
摘要： A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.
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公开(公告)号：US11568924B2
公开(公告)日：2023-01-31
申请号：US17332004
申请日：2021-05-27
发明人： Taemin Choi , Seongook Jung , Keonhee Cho
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419
摘要： An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.
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公开(公告)号：US11356098B2
公开(公告)日：2022-06-07
申请号：US17353917
申请日：2021-06-22
发明人： Byongmo Moon , Jiyoung Kim , Seongook Jung , Jongsoo Lee
IPC分类号： G11C7/10 , H03K19/173 , H03K19/0175 , G11C7/22 , H03K19/17788 , G11C7/14 , H03K19/017
摘要： A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.
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公开(公告)号：US20220148644A1
公开(公告)日：2022-05-12
申请号：US17335509
申请日：2021-06-01
发明人： Heekyung Choi , Taemin Choi , Seongook Jung , Keonhee Cho
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4094 , G11C11/4099 , G11C5/06
摘要： An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.
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9.发明公开公开(公告)号：US20240233812A1
公开(公告)日：2024-07-11
申请号：US18227355
申请日：2023-07-28
发明人： Hyunjun KIM , Sekeon Kim , Seongook Jung , Kyeongrim Baek , Keonhee Cho
IPC分类号： G11C11/4096 , G11C5/06 , G11C11/4074
CPC分类号： G11C11/4096 , G11C5/063 , G11C11/4074
摘要： A memory cell array of an SRAM including: a top memory cell array including top memory cells; and a bottom memory cell array including bottom memory cells, the top memory cells include: a first top memory cell between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline, the bottom memory cells include: a first bottom memory cell to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, and when write and read operations are not performed on the first top and bottom memory cells, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are connected to the middle node.
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公开(公告)号：US11670360B2
公开(公告)日：2023-06-06
申请号：US17335606
申请日：2021-06-01
发明人： Taemin Choi , Seongook Jung , Keonhee Cho
IPC分类号： G11C11/408 , G11C11/4094 , G11C11/4099 , G11C11/4074 , G11C5/06
CPC分类号： G11C11/4085 , G11C5/06 , G11C11/4074 , G11C11/4094 , G11C11/4099
摘要： An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first columns and including a plurality of word line assist cells in at least one second column; a plurality of word lines respectively extending on a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line assist cells; and a row driver configured to drive the plurality of word lines.
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