公开(公告)号：US11262648B2

公开(公告)日：2022-03-01

申请号：US16940590

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mun Ja Kim ,  Changyoung Jeong

IPC: G03F1/62

Abstract: A pellicle for a photomask comprises a pellicle membrane. The pellicle membrane incudes a base layer having a first surface and a second surface facing the first surface, and a first recovery layer covering the first surface of the base layer. A content of SP2 covalent bonds between carbon atoms contained in the first recovery layer is less than or equal to a content of SP2 covalent bonds between carbon atoms contained in the base layer.

公开(公告)号：US10809614B2

公开(公告)日：2020-10-20

申请号：US16214781

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mun Ja Kim ,  Changyoung Jeong

IPC: G03F1/62

Abstract: A pellicle for a photomask comprises a pellicle membrane. The pellicle membrane includes a base layer having a first surface and a second surface facing the first surface, and a first recovery layer covering the first surface of the base layer. A content of SP2 covalent bonds between carbon atoms contained in the first recovery layer is less than or equal to a content of SP2 covalent bonds between carbon atoms contained in the base layer.

公开(公告)号：US12072637B2

公开(公告)日：2024-08-27

申请号：US17971297

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/00 ,  G05B19/4097 ,  H01L21/027

CPC classification number: G03F7/705 ,  G05B19/4097 ,  H01L21/0273 ,  G05B2219/45028

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US20240036460A1

公开(公告)日：2024-02-01

申请号：US18186994

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： MUN JA KIM ,  Seung Hyun Lee ,  Jae Sun Jung ,  Byungchul Yoo ,  Byunghoon Lee ,  Changyoung Jeong ,  Deok Hyun Kim ,  Deok Hyun Cho

IPC: G03F1/62

CPC classification number: G03F1/62

Abstract: Provided herein are protective membranes for lithography that include a core layer including carbon, an interface layer on the core layer, and a protective layer on the interface layer. The interface layer includes a reactive group bonded to a carbon atom of the core layer and the reactive group includes oxygen or nitrogen. The protective layer includes an element “M”, and the element “M” is bonded to the oxygen or nitrogen of the reactive group.

公开(公告)号：US20230047588A1

公开(公告)日：2023-02-16

申请号：US17971297

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  H01L21/027 ,  G05B19/4097

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US11493850B2

公开(公告)日：2022-11-08

申请号：US16593149

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  H01L21/027 ,  G05B19/4097

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.