公开(公告)号：US20220197976A1

公开(公告)日：2022-06-23

申请号：US17173203

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Christopher P. FRASCATI ,  Simon WATERS ,  Rama S.B HARIHARA ,  David C. TANNENBAUM

IPC: G06F17/16 ,  G06F17/15 ,  G06F9/30 ,  G06N3/04 ,  G06N3/08

Abstract: A graphics processing unit (GPU) and a method is disclosed that performs a convolution operation recast as a matrix multiplication operation. The GPU includes a register file, a processor and a state machine. The register file stores data of an input feature map and data of a filter weight kernel. The processor performs a convolution operation on data of the input feature map and data of the filter weight kernel as a matrix multiplication operation. The state machine facilitates performance of the convolution operation by unrolling the data of the input feature map and the data of the filter weight kernel in the register file. The state machine includes control registers that determine movement of data through the register file to perform the matrix multiplication operation on the data in the register file in an unrolled manner.

公开(公告)号：US20210358191A1

公开(公告)日：2021-11-18

申请号：US17100796

申请日：2020-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Christopher P. FRASCATI ,  Raun M. KRISCH ,  Derek J. LENTZ ,  David C. TANNENBAUM

IPC: G06T15/00

Abstract: A GPU is disclosed, which may include a VRS interface to provide spatial information and/or primitive-specific information. The GPU may include one or more shader cores including a control logic section to determine a shading precision value based on the spatial information and/or the primitive-specific information. The control logic section may modulate a shading precision according to the shading precision value. A method for controlling shading precision by a GPU may include providing, by a VRS interface, the spatial information and/or primitive-specific information. The method may include determining, by a control logic section, a shading precision value based on the spatial information and/or the primitive-specific information. The method may include modulating a shading precision according to the shading precision value.

公开(公告)号：US20180300131A1

公开(公告)日：2018-10-18

申请号：US15633746

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： David C. TANNENBAUM ,  Srinivasan S. IYER ,  Mitchell K. ALSUP

IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/3009 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/3891 ,  G06F9/46 ,  G06T1/20 ,  G06T1/60

Abstract: A graphics processing unit may include a register file memory, a processing element (PE) and a load-store unit (LSU). The register file memory includes a plurality of registers. The PE is coupled to the register file memory and processes at least one thread of a vector of threads of a graphical application. Each thread in the vector of threads are processed in a non-stalling manner. The PE stores data in a first predetermined set of the plurality of registers in the register file memory that has been generated by processing the at least one thread and that is to be routed to a first stallable logic unit that is external to the PE. The LSU is coupled to the register file memory, and the LSU accesses the data in the first predetermined set of the plurality of registers and routes to the first stallable logic unit.

公开(公告)号：US20180196771A1

公开(公告)日：2018-07-12

申请号：US15713585

申请日：2017-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： David C. TANNENBAUM ,  Mitchell K. ALSUP ,  Srinivasan S. IYER

IPC: G06F13/366 ,  G06F13/40

CPC classification number: G06F13/366 ,  G06F13/4031

Abstract: According to one general aspect, an apparatus may include a network of node circuits and a central arbiter circuit. The network of node circuits is within an integrated circuit, wherein the network includes a plurality of segments. The central arbiter circuit may be configured to schedule a routing of a message between a pair of node circuits in the network, wherein the routing includes a guaranteed latency between the pair of node circuits.

公开(公告)号：US20180172765A1

公开(公告)日：2018-06-21

申请号：US15473593

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lawrence H. RUBIN ,  David C. TANNENBAUM

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/31704 ,  G01R31/31705 ,  G06F11/00

Abstract: According to one general aspect, an apparatus may include an interconnect bus, an interconnect-to-debug bus interface, and a debug bus. The interconnect bus may be configured to connect and manage combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock. The interconnect-to-debug bus interface may be configured to translate communications between the interconnect bus and the debug bus. The debug bus may include a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock. Each of the plurality of debug wrapper circuits may be configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus.