公开(公告)号：US10481867B2

公开(公告)日：2019-11-19

申请号：US15727093

申请日：2017-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-un Park ,  Jong-hun Lee ,  Ki-seok Kwon ,  Dong-kwan Suh ,  Kang-jin Yoon ,  Jung-uk Cho

IPC: G06F13/16 ,  G06F5/06 ,  G06F9/38 ,  G06F9/52

Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.

公开(公告)号：US10409596B2

公开(公告)日：2019-09-10

申请号：US15536351

申请日：2015-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-uk Cho ,  Suk-jin Kim ,  Dong-kwan Suh

IPC: G06F9/30 ,  G06F16/901 ,  G06F12/02 ,  G06F12/06

Abstract: Disclosed is an apparatus comprising: a plurality of memory banks; and a controller for generating a plurality of lookup tables storing data, needed for vector arithmetic operations, copied from data stored in the plurality of memory banks, and generating vector data by reading the data in the generated lookup tables.

公开(公告)号：US10396797B2

公开(公告)日：2019-08-27

申请号：US15520294

申请日：2015-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kwan Suh ,  Ki-seok Kwon ,  Young-hwan Park ,  Seung-won Lee ,  Suk-jin Kim

IPC: G06F9/38 ,  G06F15/76 ,  G06F15/173 ,  H03K19/177

Abstract: Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.

公开(公告)号：US20190114542A1

公开(公告)日：2019-04-18

申请号：US16031565

申请日：2018-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava Prasad Nagaraja ,  Dae-hyun Kim ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06N3/08 ,  G06N3/063

Abstract: An electronic apparatus and method thereof are provided for performing deep learning. The electronic apparatus includes a storage configured to store target data and kernel data; and a processor including a plurality of processing elements that are arranged in a matrix shape. The processor is configured to input, to each of the plurality of processing elements, a first non-zero element from among a plurality of first elements included in the target data, and sequentially input, to each of a plurality of first processing elements included in a first row from among the plurality of processing elements, a second non-zero element from among the plurality of elements included in the kernel data. Each of the plurality of first processing elements is configured to perform an operation between the input first non-zero element and the input second non-zero element, based on depth information of the first non-zero element and depth information of the second non-zero element.