公开(公告)号：US12062662B2

公开(公告)日：2024-08-13

申请号：US18142210

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Xu ,  Hyunkwan Yu ,  Namkyu Cho ,  Dongmyoung Kim ,  Kanghun Moon ,  Sanggil Lee ,  Sihyung Lee

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/7851

Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

公开(公告)号：US20230275091A1

公开(公告)日：2023-08-31

申请号：US18142210

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Xu ,  Hyunkwan Yu ,  Namkyu Cho ,  Dongmyoung Kim ,  Kanghun Moon ,  Sanggil Lee ,  Sihyung Lee

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/7851

Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

公开(公告)号：US20230068364A1

公开(公告)日：2023-03-02

申请号：US17718924

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Dongmyoung Kim ,  Haejun Yu ,  Ki-Hyung Ko ,  Jiho Yoo ,  Soonwook Jung

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern provided on a substrate, a source/drain pattern provided on the active pattern, a channel pattern configured to be connected to the source/drain pattern, a gate electrode configured to be extended in a first direction and to cross the channel pattern, and a first spacer provided on a side surface of the gate electrode. The first spacer includes a fence portion provided on a side surface of the active pattern and below the source/drain pattern. The source/drain pattern includes a body portion and a neck portion between the body portion and the active pattern. The body portion includes a crystalline surface configured to be slantingly extended from the neck portion. The crystalline surface is configured to be spaced apart from an uppermost portion of the fence portion.

公开(公告)号：US20220115375A1

公开(公告)日：2022-04-14

申请号：US17348962

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Xu ,  Hyunkwan Yu ,  Namkyu Cho ,  Dongmyoung Kim ,  Kanghun Moon ,  Sanggil Lee ,  Sihyung Lee

IPC: H01L27/092 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.