公开(公告)号：US08859371B2

公开(公告)日：2014-10-14

申请号：US13795839

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Geun Song ,  Ki-Hyung Ko ,  Hayoung Jeon ,  Boun Yoon ,  Jeongnam Han

IPC: H01L21/8234

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Abstract translation: 制造具有双栅极电介质层的半导体器件的方法可以包括提供包括第一和第二区域的衬底，在衬底上形成具有第一厚度的第一栅极电介质层，形成包括第一和第二沟槽的层间绝缘层， 在所述第一和第二区域中的栅介质层，在所述层间绝缘层和所述第一沟槽和所述第二沟槽的底部上形成牺牲层，形成暴露所述第一沟槽的底部的第一栅极介电层的牺牲图案，去除所述第一栅极 在所述第一沟槽的底部形成介电层，在所述第一沟槽的底部形成具有第二厚度的第二栅极介电层，去除所述牺牲图案，以及在所述第一和第二栅极电介质层中的每一个上形成栅电极。

公开(公告)号：US20190043860A1

公开(公告)日：2019-02-07

申请号：US16158797

申请日：2018-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：US10734380B2

公开(公告)日：2020-08-04

申请号：US16158797

申请日：2018-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：US20230068364A1

公开(公告)日：2023-03-02

申请号：US17718924

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Dongmyoung Kim ,  Haejun Yu ,  Ki-Hyung Ko ,  Jiho Yoo ,  Soonwook Jung

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern provided on a substrate, a source/drain pattern provided on the active pattern, a channel pattern configured to be connected to the source/drain pattern, a gate electrode configured to be extended in a first direction and to cross the channel pattern, and a first spacer provided on a side surface of the gate electrode. The first spacer includes a fence portion provided on a side surface of the active pattern and below the source/drain pattern. The source/drain pattern includes a body portion and a neck portion between the body portion and the active pattern. The body portion includes a crystalline surface configured to be slantingly extended from the neck portion. The crystalline surface is configured to be spaced apart from an uppermost portion of the fence portion.

公开(公告)号：US10714472B2

公开(公告)日：2020-07-14

申请号：US15676317

申请日：2017-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kee Sang Kwon ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49

Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

公开(公告)号：US20130244414A1

公开(公告)日：2013-09-19

申请号：US13795839

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Geun Song ,  Ki-Hyung Ko ,  Hayoung Jeon ,  Boun Yoon ,  Jeongnam Han

IPC: H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Abstract translation: 制造具有双栅极电介质层的半导体器件的方法可以包括提供包括第一和第二区域的衬底，在衬底上形成具有第一厚度的第一栅极电介质层，形成包括第一和第二沟槽的层间绝缘层， 在所述第一和第二区域中的栅介质层，在所述层间绝缘层和所述第一沟槽和所述第二沟槽的底部上形成牺牲层，形成暴露所述第一沟槽的底部的第一栅极电介质层的牺牲图案，去除所述第一栅极 在所述第一沟槽的底部形成介电层，在所述第一沟槽的底部形成具有第二厚度的第二栅极介电层，去除所述牺牲图案，以及在所述第一和第二栅极电介质层中的每一个上形成栅电极。