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公开(公告)号:US11217667B2
公开(公告)日:2022-01-04
申请号:US16806629
申请日:2020-03-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seokhoon Kim , Dongmyoung Kim , Kanghun Moon , Hyunkwan Yu , Sanggil Lee , Seunghun Lee , Sihyung Lee , Choeun Lee , Edward Namkyu Cho , Yang Xu
IPC: H01L29/08 , H01L29/78 , H01L27/088 , H01L29/06
Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.
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公开(公告)号:US11735632B2
公开(公告)日:2023-08-22
申请号:US17546690
申请日:2021-12-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seokhoon Kim , Dongmyoung Kim , Kanghun Moon , Hyunkwan Yu , Sanggil Lee , Seunghun Lee , Sihyung Lee , Choeun Lee , Edward Namkyu Cho , Yang Xu
IPC: H01L29/08 , H01L29/78 , H01L27/088 , H01L29/06
CPC classification number: H01L29/0847 , H01L27/0886 , H01L29/0653 , H01L29/0673 , H01L29/785 , H01L29/7853
Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.
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公开(公告)号:US12062662B2
公开(公告)日:2024-08-13
申请号:US18142210
申请日:2023-05-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yang Xu , Hyunkwan Yu , Namkyu Cho , Dongmyoung Kim , Kanghun Moon , Sanggil Lee , Sihyung Lee
IPC: H01L27/092 , H01L29/78
CPC classification number: H01L27/0924 , H01L29/7851
Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.
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公开(公告)号:US20230275091A1
公开(公告)日:2023-08-31
申请号:US18142210
申请日:2023-05-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yang Xu , Hyunkwan Yu , Namkyu Cho , Dongmyoung Kim , Kanghun Moon , Sanggil Lee , Sihyung Lee
IPC: H01L27/092 , H01L29/78
CPC classification number: H01L27/0924 , H01L29/7851
Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.
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公开(公告)号:US20220115375A1
公开(公告)日:2022-04-14
申请号:US17348962
申请日:2021-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yang Xu , Hyunkwan Yu , Namkyu Cho , Dongmyoung Kim , Kanghun Moon , Sanggil Lee , Sihyung Lee
IPC: H01L27/092 , H01L29/78
Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.
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公开(公告)号:US11670638B2
公开(公告)日:2023-06-06
申请号:US17348962
申请日:2021-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yang Xu , Hyunkwan Yu , Namkyu Cho , Dongmyoung Kim , Kanghun Moon , Sanggil Lee , Sihyung Lee
IPC: H01L27/092 , H01L29/78
CPC classification number: H01L27/0924 , H01L29/7851
Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.
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公开(公告)号:US20220102498A1
公开(公告)日:2022-03-31
申请号:US17546690
申请日:2021-12-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seokhoon KIM , Dongmyoung Kim , Kanghun Moon , Hyunkwan Yu , Sanggil Lee , Seunghun Lee , Sihyung Lee , Choeun Lee , Edward Namkyu Cho , Yang Xu
IPC: H01L29/08 , H01L29/78 , H01L27/088 , H01L29/06
Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.
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公开(公告)号:US20210028281A1
公开(公告)日:2021-01-28
申请号:US16806629
申请日:2020-03-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seokhoon Kim , Dongmyoung Kim , Kanghun Moon , Hyunkwan Yu , Sanggil Lee , Seunghun Lee , Sihyung Lee , Choeun Lee , Edward Namkyu Cho , Yang Xu
IPC: H01L29/08 , H01L29/78 , H01L27/088 , H01L29/06 , H01L21/8234
Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.
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