公开(公告)号：US09959835B2

公开(公告)日：2018-05-01

申请号：US15271837

申请日：2016-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon Baek ,  Hyunwook Lim ,  Kwi Sung Yoo ,  Eun-Young Jin ,  Kyongho Kim ,  JaeYoul Lee ,  Youngmin Choi

IPC: G09G5/00 ,  H03L7/08 ,  H03L7/089 ,  G09G3/20

CPC classification number: G09G5/008 ,  G09G3/2096 ,  G09G2310/027 ,  G09G2330/10 ,  G09G2370/10 ,  G09G2370/16 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/095

Abstract: A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.

公开(公告)号：US20250023664A1

公开(公告)日：2025-01-16

申请号：US18646461

申请日：2024-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyong Park ,  Kyungho Ryu ,  Yongil Kwon ,  Alankyongho Kim ,  Yong-Yun Park ,  Jung-Pil Lim ,  Hyunwook Lim

IPC: H04L1/00

Abstract: Provided is a communication system including a first electronic device and a second electronic device connected with each other through first and second channels. The second electronic device includes a reception driver generating a first internal signal based on a first data signal provided by the first electronic device through the first channel, an error detector generating an error detection signal by determining whether an error is included in the first internal signal, and an error adjuster outputting a first feedback signal through the second channel based on the error detection signal, and the first electronic device outputs a second data signal having a voltage swing width determined based on the first feedback signal through the first channel.

公开(公告)号：US12177324B2

公开(公告)日：2024-12-24

申请号：US18244107

申请日：2023-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Yun Park ,  Kyungho Ryu ,  Kilhoon Lee ,  Hyunwook Lim ,  Youngmin Choi ,  Kyungae Kim

IPC: H04L69/324 ,  H04L47/43

Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.

公开(公告)号：US12170068B2

公开(公告)日：2024-12-17

申请号：US18208543

申请日：2023-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junil Park ,  Sugyeung Kang ,  Yongil Kwon ,  Kang Joo Kim ,  Alan Kyongho Kim ,  Sunkwon Kim ,  Yong-Yun Park ,  Jung-Pil Lim ,  Hyunwook Lim

IPC: G09G3/34 ,  G09G5/00

Abstract: In a backlight apparatus, a master driving circuit generates a transmission frame including a training period including a clock training pattern and a data period including a plurality of data packets respectively corresponding to the plurality of blocks. A plurality of slave driving circuits correspond to the plurality of blocks, respectively, and are connected to the master driving circuit in a daisy chain structure. Each slave driving circuit receives the transmission frame through the daisy chain structure, recovers a clock based on the clock training pattern, and drives the plurality of light emitting elements included in a corresponding block among the plurality of blocks based on its own data packet among a plurality of data packets.

公开(公告)号：US11758030B2

公开(公告)日：2023-09-12

申请号：US17679412

申请日：2022-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Yun Park ,  Kyungho Ryu ,  Kilhoon Lee ,  Hyunwook Lim ,  Youngmin Choi ,  Kyungae Kim

IPC: H04L69/324 ,  H04L47/43

CPC classification number: H04L69/324 ,  H04L47/43

Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.

公开(公告)号：US11670258B2

公开(公告)日：2023-06-06

申请号：US17155487

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongki Kwon ,  Taewoo Kim ,  Jinyong Park ,  Hyunwook Lim ,  Woohyuk Jang ,  Hojun Chung

IPC: G09G5/10 ,  G09G3/20

CPC classification number: G09G5/10 ,  G09G3/20 ,  G09G2320/0233 ,  G09G2320/0626 ,  G09G2320/0693 ,  G09G2330/08 ,  G09G2360/145

Abstract: A method of luminance compensation includes; generating luminance compensation data based on test image data, each of the test image data corresponding to one gray level, and each of the luminance compensation data including compensation values corresponding to the one gray level, generating intra-plane data based on the luminance compensation data, one of the intra-plane data being generated based on one of the luminance compensation data, generating inter-plane stream data based on the intra-plane data, one of the inter-plane stream data being generated based on data blocks included in the intra-plane data and disposed at a same location within the intra-plane data, and sequentially storing the inter-plane stream data in a memory.

公开(公告)号：US10885870B2

公开(公告)日：2021-01-05

申请号：US16814535

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyongho Kim ,  Jinho Kim ,  Jaeyoul Lee ,  Hyunwook Lim ,  Youngmin Choi

IPC: G09G5/00

Abstract: An electronic device includes; a timing controller that generates a command to-be-sent to a display driver integrated circuit (DDI) selected from among a plurality of display driver integrated circuits (DDIs) connected to the timing controller through data lines and a shared channel The DDI is selected by a DDI control signal transferred from the timing controller to the DDI through a corresponding data line among the data lines, and the command is transferred from the timing controller to the DDI through the shared channel.

公开(公告)号：US11942061B2

公开(公告)日：2024-03-26

申请号：US18151064

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Unki Park ,  Se Whan Na ,  Hyunwook Lim ,  Woohyuk Jang

IPC: G09G5/02 ,  G09G5/10 ,  H04N23/57

CPC classification number: G09G5/10 ,  H04N23/57 ,  G09G2300/0439 ,  G09G2310/0232 ,  G09G2320/0233

Abstract: An electronic device includes a display panel that includes a first region including first pixel groups and a second region including second pixel groups, and a compensation circuit. The compensation circuit may receive first image data. The compensation circuit may compensate to generate second image data in response to a determination that the first image data corresponds to at least one of one or more particular first pixel groups that are adjacent to a boundary between the first region and the second region or one or more particular second pixel groups that are adjacent to the boundary. The compensation circuit outputs the second image data to the display panel.

公开(公告)号：US11935474B2

公开(公告)日：2024-03-19

申请号：US17957439

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Unki Park ,  Sewhan Na ,  Jonghyuk Lee ,  Hyeonsu Park ,  Hyunwook Lim

IPC: G06V40/13 ,  G09G3/3233 ,  H10K59/65

CPC classification number: G09G3/3233 ,  H10K59/65 ,  G09G2300/0439 ,  G09G2320/0686

Abstract: A display device includes a display panel including an under display camera (UDC) region and a non-UDC region, the UDC region including a plurality of sub-regions, and processing circuitry configured to, receive image data, select at least one first filter from a plurality of filters based on a spatial coordinate value of the received image data, the plurality of filters corresponding to a respective sub-region of the plurality of sub-regions, and perform first pixel rendering for the UDC region based on the at least one first filter and the image data, and the at least one first filter is generated based on a pixel arrangement pattern of the UDC region.

公开(公告)号：US11862111B1

公开(公告)日：2024-01-02

申请号：US18096352

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Whan Na ,  Jong-Hee Na ,  Byoungyoon Jang ,  Yoochae Chung ,  Hyunwook Lim

IPC: G09G3/3291 ,  G09G3/20

CPC classification number: G09G3/3291 ,  G09G3/2096 ,  G09G2310/0291 ,  G09G2320/0276 ,  G09G2320/041 ,  G09G2320/0626 ,  G09G2320/0673 ,  G09G2330/028 ,  G09G2354/00 ,  G09G2360/16

Abstract: A semiconductor device is provided. The semiconductor device includes: an offset compensation circuit configured to obtain first data including first low-order bit data, second low-order bit data and high-order bit data, select two compensation values from among a plurality of compensation values based on the first low-order bit data, identify a final compensation value by interpolating the two compensation values based on the second low-order bit data, and compensate the final compensation value to generate second data; and a source driver configured to interpolate and output two gamma voltages from among a plurality of gamma voltages based on the second data.