公开(公告)号：US20210056425A1

公开(公告)日：2021-02-25

申请号：US16910908

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwook JEONG ,  Sanghoon Myung ,  In Huh ,  Hyeonkyun Noh ,  Minchul Park ,  Hyunjae Jang

IPC: G06N3/08 ,  G06N20/00 ,  G06K9/62

Abstract: A method for a hybrid model that includes a machine learning model and a rule-based model, includes obtaining a first output from the rule-based model by providing a first input to the rule-based model, and obtaining a second output from the machine learning model by providing the first input, a second input, and the obtained first output to the machine learning model. The method further includes training the machine learning model, based on errors of the obtained second output.

公开(公告)号：US20240211736A1

公开(公告)日：2024-06-27

申请号：US18542890

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minchul Park ,  Satbyul Kim ,  Seongryeol Kim ,  Younggu Kim ,  Yeji Kim ,  Hyunjae Jang ,  In Huh

IPC: G06N3/0464 ,  G06F11/00 ,  G06N3/08

CPC classification number: G06N3/0464 ,  G06F11/004 ,  G06N3/08 ,  G06F2201/86

Abstract: Provided are an apparatus and a method of inferring semiconductor measurement results. The method of inferring semiconductor measurement results is based on artificial intelligence techniques and includes receiving layout data representing a layout of a semiconductor, generating a plurality of partial layouts based on the layout data, selecting a representative partial layout among the plurality of partial layouts, and generating, using a machine learning model, a predicted measurement result for the semiconductor based on the representative partial layout.

公开(公告)号：US11886783B2

公开(公告)日：2024-01-30

申请号：US18153573

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Myung ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

CPC classification number: G06F30/27 ,  G06F30/398 ,  G06N3/044 ,  G06N3/08 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US11669773B2

公开(公告)日：2023-06-06

申请号：US16915786

申请日：2020-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungju Kim ,  Hyojin Choi ,  In Huh ,  Jeonghoon Ko ,  Changwook Jeong ,  Younsik Park ,  Joonwan Chai

IPC: G06N20/00 ,  G06F9/30 ,  G06F9/38 ,  G06F30/3308 ,  G06F18/214

CPC classification number: G06N20/00 ,  G06F9/30036 ,  G06F9/3879 ,  G06F18/214 ,  G06F30/3308

Abstract: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

公开(公告)号：US20230142367A1

公开(公告)日：2023-05-11

申请号：US18153573

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

CPC classification number: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US20220198111A1

公开(公告)日：2022-06-23

申请号：US17692883

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Huh ,  Jeong-hoon Ko ,  Hyo-jin Choi ,  Seung-ju Kim ,  Chang-wook Jeong ,  Joon-wan Chai ,  Kwang-il Park ,  Youn-sik Park ,  Hyun-sun Park ,  Young-min Oh ,  Jun-haeng Lee ,  Tae-ho Lee

IPC: G06F30/33 ,  G06N3/08

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

公开(公告)号：US11281832B2

公开(公告)日：2022-03-22

申请号：US16788924

申请日：2020-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Huh ,  Jeong-hoon Ko ,  Hyo-jin Choi ,  Seung-ju Kim ,  Chang-wook Jeong ,  Joon-wan Chai ,  Kwang-il Park ,  Youn-sik Park ,  Hyun-sun Park ,  Young-min Oh ,  Jun-haeng Lee ,  Tae-ho Lee

IPC: G06F30/33 ,  G06N3/08

Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

公开(公告)号：US20210158152A1

公开(公告)日：2021-05-27

申请号：US16906038

申请日：2020-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-chul Park ,  Changwook Jeong

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.