公开(公告)号：US20220246624A1

公开(公告)日：2022-08-04

申请号：US17659990

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KOHJI KANAMORI ,  SEOGOO KANG ,  JONGSEON AHN ,  JEEHOON HAN

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11582

Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.

公开(公告)号：US20210193672A1

公开(公告)日：2021-06-24

申请号：US17019693

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHWAN KIM ,  YOUNGHWAN SON ,  SHINHWAN KWAN ,  JEEHOON HAN

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  H01L23/538

Abstract: A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.

公开(公告)号：US20200350330A1

公开(公告)日：2020-11-05

申请号：US16700059

申请日：2019-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGSEON AHN ,  JAERYONG SIM ,  GIYONG CHUNG ,  JEEHOON HAN

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L23/60

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.