公开(公告)号：US20190386099A1

公开(公告)日：2019-12-19

申请号：US16214659

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun KIM ,  Jae Seok YANG ,  Hae Wang LEE

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

公开(公告)号：US20170271204A1

公开(公告)日：2017-09-21

申请号：US15405762

申请日：2017-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Wook HWANG ,  Jong Hyun LEE ,  Jae Seok YANG ,  In Wook OH ,  Hyun Jae LEE

IPC: H01L21/768 ,  G06F17/50

CPC classification number: H01L21/0337 ,  H01L21/76802 ,  H01L23/481

Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.