公开(公告)号：US20190131139A1

公开(公告)日：2019-05-02

申请号：US15984614

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook OH ,  Dong Hyun KIM ,  Byung Sung KIM ,  Sung Keun PARK ,  Ho Jun CHOI

IPC: H01L21/308 ,  G06F17/50 ,  H01L21/8234

Abstract: A method of generating a layout and manufacturing a semiconductor device, including receiving a design layout of a semiconductor device including active fins; extracting a design rule of the active fins from the design layout; forming fin lines overlapping the active fins such that the fin lines have a length that is greater than a length of the active fins, wherein the fin lines continuously extend from a position adjacent to one edge of a layout region of the semiconductor device toward another edge, and are formed in an entirety of the layout region of the semiconductor device; forming a mandrel pattern layout in an entirety of the layout region of the semiconductor device, using the fin lines; and forming a cut pattern layout in the entirety of the layout region of the semiconductor device, using the active fins.

公开(公告)号：US20180182758A1

公开(公告)日：2018-06-28

申请号：US15902025

申请日：2018-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook OH ,  Jae Seok YANG ,  Jong Hyun LEE ,  Hyun Jae LEE ,  Sung Wook HWANG

IPC: H01L27/088 ,  H01L27/02 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L27/0886 ,  G06F17/5072 ,  H01L23/528 ,  H01L27/0207

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

公开(公告)号：US20190051600A1

公开(公告)日：2019-02-14

申请号：US15873352

申请日：2018-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Wook OH ,  Dong Hyun KIM ,  Doo Hwan PARK ,  Sung Keun PARK ,  Chul Hong PARK ,  Sung Wook HWANG

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.

公开(公告)号：US20170271204A1

公开(公告)日：2017-09-21

申请号：US15405762

申请日：2017-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Wook HWANG ,  Jong Hyun LEE ,  Jae Seok YANG ,  In Wook OH ,  Hyun Jae LEE

IPC: H01L21/768 ,  G06F17/50

CPC classification number: H01L21/0337 ,  H01L21/76802 ,  H01L23/481

Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.

公开(公告)号：US20190198496A1

公开(公告)日：2019-06-27

申请号：US16255519

申请日：2019-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook OH ,  Jae Seok YANG ,  Jong Hyun LEE ,  Hyun Jae LEE ,  Sung Wook HWANG

IPC: H01L27/088 ,  H01L27/02 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L27/0886 ,  G06F17/5072 ,  H01L23/528 ,  H01L27/0207

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

公开(公告)号：US20170287909A1

公开(公告)日：2017-10-05

申请号：US15372840

申请日：2016-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook OH ,  Jae Seok YANG ,  Jong Hyun LEE ,  Hyun Jae LEE ,  Sung Wook HWANG

IPC: H01L27/088 ,  G06F17/50 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0886 ,  G06F17/5072 ,  H01L23/528 ,  H01L27/0207

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.