Antenna module and electronic device including the same

    公开(公告)号:US11955699B2

    公开(公告)日:2024-04-09

    申请号:US17568128

    申请日:2022-01-04

    CPC classification number: H01Q1/243 H01Q9/0407

    Abstract: An electronic device is provided. The electronic device includes a housing including a side member, a support member, a display, an antenna module including one or more patch antennas, a printed circuit board (PCB), a wireless communication circuit disposed on the PCB, a first conductive member, a first connector, a second connector, and a protrusion extending from the first end of the first conductive member toward an interior of the housing, and electrically connected to the first conductive member. The antenna module is disposed at locations corresponding to a first opening defined by the first conductive member, the support member, the first connector, and the second connector, and a second opening defined by the first conductive member, the support member, the first connector, and the protrusion, and the wireless communication circuit is electrically connected to the protrusion and the antenna module.

    Antenna and electronic device including the same

    公开(公告)号:US11949149B2

    公开(公告)日:2024-04-02

    申请号:US17511910

    申请日:2021-10-27

    CPC classification number: H01Q1/24 H01Q1/38 H04B1/38

    Abstract: According to various embodiments, an electronic device includes: a first housing including a first area, a second housing coupled to be slidable in a first direction from the first housing and including a second area overlapping the first area in a slide-in state, an antenna structure disposed in the first housing to overlap the first area when the first housing is viewed from the top, a conductive part disposed in the second area and electromagnetically connected to the antenna structure in the slide-in state, and wireless communication circuitry electrically connected to the antenna structure. The wireless communication circuitry may be configured to transmit and/or receive radio signals in at least one designated frequency band through the antenna structure and the conductive part in the slide-in state.

    SEMICONDUCTOR MEMORY DEVICES WITH ERROR CORRECTION

    公开(公告)号:US20250130891A1

    公开(公告)日:2025-04-24

    申请号:US18657360

    申请日:2024-05-07

    Abstract: A memory system includes a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device includes a memory cell array that is divided into a plurality of sub array blocks arranged in a first direction and a second direction. The memory controller includes an error correction code (ECC) engine. The ECC engine, in a write operation, generates a parity data by performing an ECC encoding on a user data including a plurality of sub data units, generates a main data by interleaving the sub data units based on mapping information such that two sub data units to be stored in one row of a target sub array block are included in one symbol. The mapping information indicates a mapping relationship between the plurality of sub data units and rows of the target sub array block storing the plurality of sub data units.

    Electronic device including flexible display

    公开(公告)号:US12279388B2

    公开(公告)日:2025-04-15

    申请号:US17568862

    申请日:2022-01-05

    Abstract: According to an embodiment of the disclosure, an electronic device may include: a housing including a first housing and a second housing configured to be slidable with respect to the first housing, and a flexible display including a first area visible to the outside of the electronic device and a second area configured to extend from the first area such that, based on sliding of the second housing, the second area is moved out of the housing or is moved into an inner space of the housing, wherein the housing comprises a conductive part facing a front surface of the flexible display, and the conductive part is electrically connected to a conductive layer forming a rear surface of the flexible display or is positioned on the rear surface.

    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME

    公开(公告)号:US20240178861A1

    公开(公告)日:2024-05-30

    申请号:US18339490

    申请日:2023-06-22

    CPC classification number: H03M13/1111 H03M13/611

    Abstract: A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.

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