MEMORY CONTROLLERS AND MEMORY SYSTEMS
    1.
    发明公开

    公开(公告)号:US20240281323A1

    公开(公告)日:2024-08-22

    申请号:US18469894

    申请日:2023-09-19

    CPC classification number: G06F11/1044

    Abstract: A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip includes an error correction code (ECC) engine, the ECC engine including an ECC decoder to correct Q symbols errors in a codeword set read from the memory module, Q is a maximum natural number equal to or less than P and P is a natural number equal to or greater than four. The ECC decoder is configured to generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix and to perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols.

    Antenna and electronic device comprising same

    公开(公告)号:US12218439B2

    公开(公告)日:2025-02-04

    申请号:US17863996

    申请日:2022-07-13

    Abstract: An electronic device is provided. The electronic device includes a housing including a conductive member on which at least one power supply point and ground point are positioned, at least one ground member arranged inside the housing, a first ground path connecting the ground point to the ground member, a second ground path connecting the ground point to the ground member, a printed circuit board (PCB) arranged inside the housing and a processor arranged on the PCB. The processor is configured to supply power to the at least one power supply point so that the conductive member transmits and/or receives a signal of a first frequency band.

    Electronic device having structure for eliminating parasitic emission

    公开(公告)号:US11316266B2

    公开(公告)日:2022-04-26

    申请号:US17106778

    申请日:2020-11-30

    Abstract: An electronic device for minimizing parasitic emission is provided. The electronic device includes a housing including a front cover, a rear cover located on the opposite side of the front cover, and a lateral member surrounding a space between the front cover and the rear cover, the lateral member having a first conductive portion formed on at least a portion thereof, a support member disposed in the space of the housing and including a second conductive portion having therein at least one opening, a display including a conductive sheet that is disposed between the front cover and the support member so as to be visible from an outside through at least a part of the front cover and is disposed to face the support member, and a wireless communication circuit electrically connected to the first conductive portion. The conductive sheet includes a first portion, a second portion disposed adjacent to the first portion, and a coupling that is partly connected between the first portion and the second portion. In case the front cover is viewed from above, the coupling is disposed at a position overlapping the opening.

    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME

    公开(公告)号:US20240178861A1

    公开(公告)日:2024-05-30

    申请号:US18339490

    申请日:2023-06-22

    CPC classification number: H03M13/1111 H03M13/611

    Abstract: A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.

    Antenna module and electronic device including the same

    公开(公告)号:US12255383B2

    公开(公告)日:2025-03-18

    申请号:US18624631

    申请日:2024-04-02

    Abstract: An electronic device is provided. The electronic device includes a housing including a side member, a support member, a display, an antenna module including one or more patch antennas, a printed circuit board (PCB), a wireless communication circuit disposed on the PCB, a first conductive member, a first connector, a second connector, and a protrusion extending from the first end of the first conductive member toward an interior of the housing, and electrically connected to the first conductive member. The antenna module is disposed at locations corresponding to a first opening defined by the first conductive member, the support member, the first connector, and the second connector, and a second opening defined by the first conductive member, the support member, the first connector, and the protrusion, and the wireless communication circuit is electrically connected to the protrusion and the antenna module.

    MEMORY SYSTEM, METHOD OF OPERATING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20240385925A1

    公开(公告)日:2024-11-21

    申请号:US18543737

    申请日:2023-12-18

    Abstract: A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller includes a plurality of volatile memory devices; and a memory controller configured to control the plurality of volatile memory devices, wherein the memory controller includes: a host interface configured to communicate with a host device based on a Compute eXpress Link (CXL) communication protocol; an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level being error correction levels based on cell reliability information and data reliability request information which are associated with the cache line data; and an ECC engine configured to, based on the ECC control signal indicating the first correction level, generate first parity symbols associated with the cache line data, and based on the ECC control signal indicating the second correction level, generate additional parity symbols.

    Semiconductor fabrication process and method of optimizing the same

    公开(公告)号:US11791184B2

    公开(公告)日:2023-10-17

    申请号:US17719722

    申请日:2022-04-13

    Abstract: The program code, when executed by a processor, causes the processor to input fabrication data including a plurality of parameters associated with a semiconductor fabricating process to a framework to generate a first class for analyzing the fabrication data, to extract a first parameter targeted for analysis and a second parameter associated with the first parameter from the plurality of parameters and generate a second class for analyzing the first parameter as a sub class of the first class, to modify the first parameter and the second parameter into a data structure having a format appropriate to store in the second class, so as to be stored in the second class, to perform data analysis on the first parameter and the second parameter, to transform the first parameter and the second parameter into corresponding tensor data, and to input the tensor data to the machine learning model.

    Antenna and electronic device including same

    公开(公告)号:US12136770B2

    公开(公告)日:2024-11-05

    申请号:US17860850

    申请日:2022-07-08

    Abstract: An electronic device includes a housing including an internal space, a display disposed in the internal space, the display being visible from an outside of the electronic device through at least a part of the housing, at least one first antenna disposed in the internal space, a second antenna disposed in the internal space and wound multiple times and including a conductive pattern disposed to be spaced apart from the first antenna, a first wireless communication circuit configured to transmit or receive a wireless signal in a first frequency band via the at least one first antenna, and a second wireless communication circuit configured to transmit or receive a wireless signal in a second frequency band via the second antenna, wherein the at least one first antenna is spaced apart by a distance from the conductive pattern.

    Electronic device comprising antenna

    公开(公告)号:US12126095B2

    公开(公告)日:2024-10-22

    申请号:US17971165

    申请日:2022-10-21

    CPC classification number: H01Q5/314 H01Q1/243 H01Q1/38 H04B7/0413

    Abstract: An electronic device includes: a side member forming sides of the electronic device, the side member including a first conductive portion, a second conductive portion, a first non-conductive portion, and a slit; a printed circuit board including the ground; and a wireless communication circuit, wherein the first conductive portion includes a first electrical path and a second electrical path, the second conductive portion includes a third electrical path and a fourth electrical path, a capacitor is arranged along the third electrical path, and the wireless communication circuit may feed, to the first conductive portion via the first electrical path, an RF signal of a first frequency band and may feed, to the second conductive portion via the third electrical path, an RF signal of a second frequency band which at least partially overlaps the first frequency band.

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