公开(公告)号：US20240185942A1

公开(公告)日：2024-06-06

申请号：US18482300

申请日：2023-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Sunghye Cho ,  Daehyun Kim ,  Kyomin Sohn ,  Kijun Lee

IPC: G11C29/42 ,  G11C29/14

CPC classification number: G11C29/42 ,  G11C29/14

Abstract: A memory device includes a memory cell array and an error correction code (ECC) circuit. The ECC circuit, which is configured to correct an error in a data code read out from the memory cell array, includes: (i) a syndrome calculating unit configured to operate a plurality of syndromes based on the data code and an H-matrix, (ii) an error location detecting unit configured to generate an error vector based on the plurality of syndromes, and (iii) an error correcting unit configured to correct an error within the data code based on the error vector, and output corrected data.

公开(公告)号：US20250036521A1

公开(公告)日：2025-01-30

申请号：US18770435

申请日：2024-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Jae-Gon Lee ,  Kyomin Sohn ,  Yeonggeol Song ,  Kijun Lee

IPC: G06F11/10

Abstract: An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.

公开(公告)号：US20240385925A1

公开(公告)日：2024-11-21

申请号：US18543737

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Daehyun Kim ,  Jiho Kim ,  Kyomin Sohn ,  Kijun Lee ,  Sunghye Cho

IPC: G06F11/10 ,  G06F11/00 ,  G06F11/07

Abstract: A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller includes a plurality of volatile memory devices; and a memory controller configured to control the plurality of volatile memory devices, wherein the memory controller includes: a host interface configured to communicate with a host device based on a Compute eXpress Link (CXL) communication protocol; an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level being error correction levels based on cell reliability information and data reliability request information which are associated with the cache line data; and an ECC engine configured to, based on the ECC control signal indicating the first correction level, generate first parity symbols associated with the cache line data, and based on the ECC control signal indicating the second correction level, generate additional parity symbols.

公开(公告)号：US20240281323A1

公开(公告)日：2024-08-22

申请号：US18469894

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Jiho Kim ,  Kijun Lee ,  Kyomin Sohn

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip includes an error correction code (ECC) engine, the ECC engine including an ECC decoder to correct Q symbols errors in a codeword set read from the memory module, Q is a maximum natural number equal to or less than P and P is a natural number equal to or greater than four. The ECC decoder is configured to generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix and to perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols.

公开(公告)号：US20240178861A1

公开(公告)日：2024-05-30

申请号：US18339490

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Kim ,  Seongmuk Kang ,  Daehyun Kim ,  Kijun Lee ,  Myungkyu Lee ,  Kyomin Sohn ,  Sunghye Cho

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1111 ,  H03M13/611

Abstract: A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.