公开(公告)号：US11329066B2

公开(公告)日：2022-05-10

申请号：US17201494

申请日：2021-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Soonmoon Jung ,  Daewon Ha

IPC: H01L27/12 ,  H01L29/08 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

Abstract: A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.

公开(公告)号：US20250098224A1

公开(公告)日：2025-03-20

申请号：US18967518

申请日：2024-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee Park ,  Munhyeon Kim ,  Uihui Kwon ,  Joohyung You ,  Daewon Ha

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

Abstract: A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

公开(公告)号：US12191368B2

公开(公告)日：2025-01-07

申请号：US17455681

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee Park ,  Munhyeon Kim ,  Uihui Kwon ,  Joohyung You ,  Daewon Ha

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

Abstract: A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

公开(公告)号：US12159939B2

公开(公告)日：2024-12-03

申请号：US17724619

申请日：2022-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Doyoung Choi ,  Daewon Ha ,  Mingyu Kim

IPC: H01L29/786

Abstract: A semiconductor device includes an active pattern on a substrate, a plurality of source/drain patterns in a first direction on the active pattern, a first channel structure between a pair of source/drain patterns, a second channel structure between another pair of source/drain patterns, a first gate electrode extending in a second direction perpendicular to the first direction, and a second gate electrode intersecting the second channel structure and extending in the second direction. The first gate electrode includes a first portion between a bottom surface of the first channel structure and a top surface of the active pattern, and the second gate electrode includes a first portion between a bottom surface of the second channel structure and the top surface of the active pattern. A thickness of the first portion of the second gate electrode is greater than a thickness of the first portion of the first gate electrode.

公开(公告)号：US20240178229A1

公开(公告)日：2024-05-30

申请号：US18430902

申请日：2024-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

公开(公告)号：US11908861B2

公开(公告)日：2024-02-20

申请号：US17394580

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

公开(公告)号：US20220181323A1

公开(公告)日：2022-06-09

申请号：US17394580

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Mingyu Kim ,  Doyoung Choi ,  Daewon Ha

IPC: H01L27/092

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.