公开(公告)号：US20230080400A1

公开(公告)日：2023-03-16

申请号：US18051034

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： KEUN HWI CHO ,  Soonmoon Jung ,  Dongwon Kim ,  Myung Gil Kang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/417 ,  H01L23/528

Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.

公开(公告)号：US11798949B2

公开(公告)日：2023-10-24

申请号：US17712571

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Soonmoon Jung ,  Daewon Ha

IPC: H01L27/12 ,  H01L29/08 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42368

Abstract: A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.

公开(公告)号：US11171136B2

公开(公告)日：2021-11-09

申请号：US16849238

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Soonmoon Jung

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/18 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer.

公开(公告)号：US11978805B2

公开(公告)日：2024-05-07

申请号：US18110961

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78645 ,  H01L29/66484 ,  H01L29/6675 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/78696

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US11004981B2

公开(公告)日：2021-05-11

申请号：US16504960

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US11855165B2

公开(公告)日：2023-12-26

申请号：US18051034

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi Cho ,  Soonmoon Jung ,  Dongwon Kim ,  Myung Gil Kang

IPC: H01L29/423 ,  H01L23/528 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L29/42356 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/42376

Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.

公开(公告)号：US11489055B2

公开(公告)日：2022-11-01

申请号：US17192959

申请日：2021-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi Cho ,  Soonmoon Jung ,  Dongwon Kim ,  Myung Gil Kang

IPC: H01L29/423 ,  H01L27/092 ,  H01L23/528 ,  H01L29/417

Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.

公开(公告)号：US20220223626A1

公开(公告)日：2022-07-14

申请号：US17712571

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Soonmoon Jung ,  Daewon Ha

IPC: H01L27/12 ,  H01L29/08 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

Abstract: A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.

公开(公告)号：US11329066B2

公开(公告)日：2022-05-10

申请号：US17201494

申请日：2021-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Soonmoon Jung ,  Daewon Ha

IPC: H01L27/12 ,  H01L29/08 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

Abstract: A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.

公开(公告)号：US12068321B2

公开(公告)日：2024-08-20

申请号：US18347023

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Soonmoon Jung

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/18 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/187 ,  H01L21/28088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer.