公开(公告)号：US11798949B2

公开(公告)日：2023-10-24

申请号：US17712571

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Soonmoon Jung ,  Daewon Ha

IPC: H01L27/12 ,  H01L29/08 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42368

Abstract: A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.

公开(公告)号：US11749678B2

公开(公告)日：2023-09-05

申请号：US17844807

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Youngchai Jung ,  Mingyu Kim ,  Seon-Bae Kim ,  Yeonho Park

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/0649 ,  H01L29/7827

Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

公开(公告)号：US12225703B2

公开(公告)日：2025-02-11

申请号：US18479323

申请日：2023-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mingyu Kim ,  Munhyeon Kim ,  Daewon Ha

IPC: H10B10/00 ,  G11C11/412 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device includes forming a first sacrificial and first active layer on a substrate; forming a first mask pattern on a portion of the substrate; etching the first sacrificial and first active layer partially using the first mask pattern to expose a portion of a top surface of the substrate; forming a semiconductor layer on the exposed top surface of the substrate; forming sacrificial layers and active layers on the first active and semiconductor layer, the active layers including an uppermost second active layer; forming a second mask pattern on a portion of the second active layer; forming a trench using the second mask pattern, the trench defining a first and second active pattern; and removing the sacrificial layers to form a first and second channel patterns on the first and second active patterns, respectively, wherein the first active pattern includes the semiconductor layer.

公开(公告)号：US20190198636A1

公开(公告)日：2019-06-27

申请号：US16015852

申请日：2018-06-22

Applicant: Samsung Electronics Co., Ltd

Inventor： Changwoo Noh ,  Munhyeon Kim ,  Hansu Oh ,  Sungman Whang ,  Dongwon Kim

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/31144 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer.

公开(公告)号：US12199163B2

公开(公告)日：2025-01-14

申请号：US18478373

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Myung Gil Kang ,  Wandon Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US11804530B2

公开(公告)日：2023-10-31

申请号：US17245601

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Myung Gil Kang ,  Wandon Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42364 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78696

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US11257925B2

公开(公告)日：2022-02-22

申请号：US16836138

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwoo Noh ,  Munhyeon Kim ,  Hansu Oh ,  Sungman Whang ,  Dongwon Kim

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/165 ,  H01L21/311

Abstract: Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer.

公开(公告)号：US11832430B2

公开(公告)日：2023-11-28

申请号：US17363748

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mingyu Kim ,  Munhyeon Kim ,  Daewon Ha

IPC: H10B10/00 ,  H01L29/10 ,  G11C11/412

CPC classification number: H10B10/12 ,  G11C11/412 ,  H01L29/1033

Abstract: A semiconductor device may include a pull-down transistor and a pull-up transistor disposed on a substrate. Each of the pull-down transistor and the pull-up transistor may include an active pattern disposed on the substrate; two source/drain patterns disposed on the active pattern; a channel pattern interposed between the two source/drain patterns, the channel pattern including semiconductor patterns that are disposed in a noncontiguous stack, such that a semiconductor pattern does not contact an adjacent semiconductor pattern; and a gate electrode crossing the channel pattern in a first direction. There may be more or less semiconductor patterns of the pull-down transistor as compared to semiconductor patterns of the pull-up transistor.

公开(公告)号：US20220285511A1

公开(公告)日：2022-09-08

申请号：US17455681

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee Park ,  Munhyeon Kim ,  Uihui Kwon ,  Joohyung You ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

公开(公告)号：US20220223626A1

公开(公告)日：2022-07-14

申请号：US17712571

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Soonmoon Jung ,  Daewon Ha

IPC: H01L27/12 ,  H01L29/08 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

Abstract: A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.