公开(公告)号：US20150378885A1

公开(公告)日：2015-12-31

申请号：US14668015

申请日：2015-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNJIN KIM ,  KITAE PARK ,  SEONKYOO LEE ,  JEONGDON IHM ,  YOUNGJIN JEON

IPC: G06F12/02 ,  G11C16/10 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F12/0246 ,  G06F13/1673 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/1072 ,  G11C16/102

Abstract: A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor.

Abstract translation: 固态驱动器包括非易失性存储器，随机存取存储器和存储器控制器。 非易失性存储器包含多个非易失性存储器芯片和缓冲芯片。 存储器控制器由内部总线，主机接口，存储器接口，缓冲器控制电路和处理器构成。

公开(公告)号：US20150364173A1

公开(公告)日：2015-12-17

申请号：US14665148

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNJIN KIM ,  SEONKYOO LEE ,  JEONGDON IHM ,  YOUNGJIN JEON

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C16/06 ,  G11C16/32

Abstract: A storage device includes a nonvolatile memory, and a memory controller adapted to control the nonvolatile memory and to transmit a first timing signal to the nonvolatile memory at a read operation. The nonvolatile memory includes a nonvolatile memory device adapted to output read data and a second timing signal in response to the first timing signal, and a retiming circuit adapted to detect a locking delay according to the first timing signal, to produce a third timing signal from the second timing signal using the detected locking delay, to retime the read data by latching the read data in synchronization with the third timing signal and to output the third timing signal and the retimed read data to the memory controller.

Abstract translation: 存储装置包括非易失性存储器和适于在读取操作时控制非易失性存储器并将第一定时信号发送到非易失性存储器的存储器控​​制器。 非易失性存储器包括适于响应于第一定时信号输出读取数据和第二定时信号的非易失性存储器件，以及适于根据第一定时信号检测锁定延迟的重定时电路，以产生来自 使用检测到的锁定延迟的第二定时信号，通过与第三定时信号同步地锁存读取的数据来重新读取数据，并将第三定时信号和重新定时的读取数据输出到存储器控制器。