公开(公告)号：US09576978B2

公开(公告)日：2017-02-21

申请号：US14042900

申请日：2013-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Sang-Kyu Oh

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/6681

Abstract: A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins.

Abstract translation: 半导体集成电路（IC）可以包括至少一个包括至少一个鳍状场效应晶体管（FET）的单元。 至少一个电池可以包括沿着第一方向延伸并且沿垂直于第一方向的第二方向彼此平行布置的多个散热片。 第二方向上的至少一个单元的尺寸可以对应于多个翅片的数量和间距。

公开(公告)号：US09576953B2

公开(公告)日：2017-02-21

申请号：US14488628

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Hyun Baek ,  Jin-Hyun Noh ,  Tae-Joong Song ,  Gi-Young Yang ,  Sang-Kyu Oh

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L27/11 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G06F17/5068 ,  H01L27/1104 ,  H01L29/785 ,  H01L29/7851

Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.

Abstract translation: 用于设计半导体器件的布局设计系统包括处理器，存储中间设计的存储模块和由处理器用于校正中间设计的校正模块。 中间设计包括有源区域和有源区域的虚拟设计。 每个虚拟设计包括虚拟结构和设置在虚拟结构的相对侧的虚设间隔物。 校正模块被配置为改变至少一些虚拟设计的区域的宽度。 校正后的设计用于制造具有活性鳍片，设置在活性鳍片上的硬掩模层，与硬掩模层之间交叉的栅极结构以及设置在栅极结构的至少一侧上的间隔物的半导体器件。 硬掩模层和活动翅片具有由于虚拟设计而变化的宽度。