公开(公告)号：US09905561B2

公开(公告)日：2018-02-27

申请号：US15409523

申请日：2017-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

IPC: H01L23/52 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  G06F17/50

CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

公开(公告)号：US09716106B2

公开(公告)日：2017-07-25

申请号：US15232223

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Sang-kyu Oh ,  Jung-Ho Do ,  Sun-young Park ,  Seung-young Lee ,  Hyo-sig Won

IPC: H01L27/118 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

公开(公告)号：US20180175024A1

公开(公告)日：2018-06-21

申请号：US15686795

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L27/088 ,  H01L21/823487 ,  H01L21/823885 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/7827

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

公开(公告)号：US11164863B2

公开(公告)日：2021-11-02

申请号：US16732670

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/8234

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

公开(公告)号：US20160055286A1

公开(公告)日：2016-02-25

申请号：US14820983

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Sang-kyu Oh ,  Seung-young Lee

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G03F1/00 ,  G06F17/5072 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Abstract translation: 设计集成芯片（IC）的布局的方法包括通过放置和布线定义IC的多个标准单元来设计第一布局，以及通过在与...相关的掩模数据准备处理过程中修改第一布局来生成第二布局 第一布局，其中通过连接与第一布局的第一层相对应的第一层图案中的第一和第二图案来生成第二布局，使得形成第一层图案所需的掩模的数量减少。

公开(公告)号：US20200051977A1

公开(公告)日：2020-02-13

申请号：US16444252

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-young Lim ,  Jae-ho Park ,  Sang-hoon Baek ,  Hyeon-gyu You ,  Dal-hee Lee

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/535

Abstract: Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.

公开(公告)号：US09436792B2

公开(公告)日：2016-09-06

申请号：US14820983

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Sang-kyu Oh ,  Seung-young Lee

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G03F1/00

CPC classification number: G06F17/5077 ,  G03F1/00 ,  G06F17/5072 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Abstract translation: 设计集成芯片（IC）的布局的方法包括通过放置和布线定义IC的多个标准单元来设计第一布局，以及通过在与...相关的掩模数据准备处理过程中修改第一布局来生成第二布局 第一布局，其中通过连接与第一布局的第一层相对应的第一层图案中的第一和第二图案来生成第二布局，使得形成第一层图案所需的掩模的数量减少。

公开(公告)号：US09299842B2

公开(公告)日：2016-03-29

申请号：US14026345

申请日：2013-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek

IPC: H01L29/76 ,  H01L29/78 ,  G06F17/50 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/785 ,  G06F17/5063 ,  G06F17/5081 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/6681

Abstract: Provided are a fin transistor including a plurality of fins and a semiconductor integrated circuit including a plurality of fin transistors. A width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on the electrical characteristics of the fin transistor.

Abstract translation: 提供了包括多个鳍片的翅片晶体管和包括多个鳍式晶体管的半导体集成电路。 多个翅片中的至少一个翅片的宽度与其他翅片的宽度不同，并且基于鳍式晶体管的电特性单独确定多个翅片的每个宽度。

公开(公告)号：US20160055284A1

公开(公告)日：2016-02-25

申请号：US14801239

申请日：2015-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Jae-ho Park ,  Gi-young Yang ,  Jin-tae Kim ,  Hyo-sig Won

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

Abstract: A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.

Abstract translation: 标准单元库及其使用方法可以包括关于存储在非暂时计算机可读存储介质上的多个标准单元的信息，其中多个标准单元中的至少一个包括一个引脚，通过该引脚输入信号 或者至少一个标准单元的输出信号通过并包括垂直于堆叠方向的第一和第二区域。 当通孔设置在销中时，第二区域可以提供通孔的电阻值小于第一区域的电阻值。 标准单元库还可以包括对应于第二区域的标记信息。

公开(公告)号：US11101267B2

公开(公告)日：2021-08-24

申请号：US16444252

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-young Lim ,  Jae-ho Park ,  Sang-hoon Baek ,  Hyeon-gyu You ,  Dal-hee Lee

IPC: H01L27/088 ,  H01L23/535 ,  H01L29/06 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8234 ,  H02M7/00

Abstract: Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.